Software Tools

Digital logic courses use the Quartus® Prime Lite Edition, and also the ModelSim®-Altera Starter Edition software. Computer organization and embedded systems courses use the Quartus Prime Lite Edition and also the Altera® Monitor Program. To learn more, read the sections below.

The Quartus software is a complete CAD system for designing digital circuits. For use in teaching, the FPGA University Program recommends the Quartus Prime Lite Edition software, which does not require a license. The licensed commercial version of the Quartus Prime Standard and Pro Edition software is available for installation in university laboratory facilities.

To download the Quartus software, click here. The table below shows the latest version of the Quartus software that supports each of our FPGA boards.

Board Quartus Version
DE10-Standard 16.1
DE10-Lite 16.1
DE10-Nano 16.1
DE5 16.1
DE4 16.1
DE3 13.1
DE2-115 16.1
DE2-70 13.0
DE2 13.0
DE1-SoC 16.1
DE1 13.0
DE0-Nano-SoC 16.1
DE0-Nano 16.1
DE0-CV 16.1
DE0 13.1

The Quartus software comes with a Vector Waveform Editor tool to allow users to draw the test input signals for simulation and select which signal should be shown in the simulation results. The method of running the Waveform Editor tool has varied over the various releases of the Quartus software. A brief discription of the Waveform Editor tool with regards to different versions of the Quartus software is given below. For more information, please see the FPGA University Program tutorial "Introduction to Quartus Simulation".

 

Starting with Quartus software v13.0, the Waveform Editor tool for performing simulations can be opened from within the Quartus software. This is accomplished by selecting “File -> New -> University Program VWF”. Test vectors created with this tool can be used in simulation of your circuits by running the ModelSim-Altera simulation tool. The simulator can be started from within the Waveform Editor, or by using the Altera Nativelink flow.

 

For Quartus software v10.1 through 12.1, the Waveform Editor tool could be used only to enter test inputs and set output signals to view. Running simulations was done using a separate tool, Qsim. For Quartus software v10.1 and 11.0, the QSim tool and Waveform Editor must be installed separately by using the FPGA University Program Installer. Beginning with the Quartus software v11.1, the QSim tool and Waveform Editor are bundled with the Quartus software. The QSim tool can be invoked from a command window by using the command "quartus_sh --qsim". The quartus_sh executable is part of the Quartus software. It can be found in the folder where the Quartus software is installed, for example C:\altera\12.0\quartus\bin. For this example of an installation folder you would type the command C:\altera\12.0\quartus\bin\quartus_sh --qsim. Note that if you are using the Quartus II Subscription Edition software and you are running a 64 bit operating system, then the executable is found in quartus\bin64\.

 

For Quartus software v9.1 and earlier, the Waveform Editor tool was included with the Quartus software and used the internal Quartus simulator.

 

ModelSim is a widely-used logic simulation tool for verification and debugging of digital circuits. Intel provides a version of the ModelSim software, which includes libraries for Intel's FPGAs. You can download the ModelSim program along with the Quartus software.

The Qsys system integration tool is used for designing and implementing embedded computer systems. It facilitates the creation of embedded systems that include processors, memory interfaces, and a variety of I/O devices. The Qsys tool is included as a part of the Quartus software.

The Monitor Program allows students to easily compile and debug both assembly language and C programs. It supports both the ARM* Cortex*-A9 and Nios® II processors. The Monitor Program includes standard debugging features such as single-step, breakpoints, register and memory display, and so on.

This software is available as part of the FPGA University Program Installer. The suite also contains the FPGA University Program intellectual property (IP) cores and example computer systems.

The University Program Installer contains the Monitor Program and example computer systems. Depending on the selected version, the installer additionally contains the Intel FPGA University Program IP Cores or their patches (see the University Program IP Core section above for more details).

We provide SD card images containing an Ubuntu-based Linux distribution for use with our SoC-based DE-series boards. The Linux distribution can be used for embedded Linux exercises and projects. Features include:

  • Command line interface through serial UART or SSH
  • Desktop interface through VNC connection
  • Command line FPGA programming capability
  • Automatic FPGA programming at boot up, using the default Computer system for the board (the same system that is included with the Intel FPGA Monitor Program)
  • Built-in GCC toolchain for compiling code natively on the board
  • Sample applications that demonstrate FPGA communication and driver development
  • OpenCL support for our boards that have the OpenCL BSP

To get started, refer to the tutorial Using Linux on the DE1-SoC and download the appropriate SD card image from the list in the table below.

The Intel® FPGA SDK for Open Computing Language (OpenCL™) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, pushing the longer compile time to the end when you are pleased with your kernel code results. Leverage prewritten optimized OpenCL or register transfer level (RTL) functions, calling them from the host or directly from within your OpenCL kernels.

Intel® High-Level Synthesis (HLS) Compiler accelerates FPGA design by enabling hardware developers to work at higher levels of abstraction using untimed C/C++. Simulation times for abstract models developed in C/C++ typically finish in seconds vs register transfer level (RTL) simulations that can take minutes or hours. Intel HLS Compiler generates production quality RTL that is device optimized for Intel FPGAs.

DSP Builder for Intel FPGAs is a tool for designing systems for digital signal processing (DSP). It contains a library of modules that can be used in the industry-standard MathWorks/Simulink tools. The DSP Builder is available free of charge for universities.


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