EDA Partners

Our EDA ecosystem ensures that you have a complete design solution in designing, verifying, and integrating Intel® FPGAs into your systems. 

システム・レベル設計パートナー

EDA ベンダー 製品名 デザイン・ソリューション
Altium Altium Designer High-level design tool
Agnisys Technology Pvt Ltd IDesignSpec Register map management
Bluespec Bluespec Compiler High-level synthesis
Cadence Design Systems,Inc. C-to-Silicon Compiler High-level synthesis
Duolog Technologies Socrates Register map management
Impulse Accelerated Technologies ImpulseC CoDeveloper

High-level synthesis and simulation

NEC CyberWorkBench High-level synthesis
PDTi SpectaReg Register map management
Poseidon Design Systems Triton Tuner System-level simulation
Triton Builder High-level synthesis
SynaptiCAD TestBencher Pro

High-level design tool

Synopsys Synphony Model Compiler High-level synthesis solution

デザイン設計パートナー

EDA ベンダー 製品名 デザイン・ソリューション
Mentor Graphics® HDL Designer Project management, design entry, and analysis tool
Sigasi Sigasi HDT Design entry, code comprehension, project management, and collaboration

シンセシス・パートナー

EDA ベンダー 製品名 デザイン・ソリューション

Mentor Graphics

Precision RTL

Logic synthesis

Precision RTL Plus

Advanced logic synthesis

Precision Physical

Timing closure tool

Synopsys

Synplify Pro

Logic synthesis tool

Synplify Premier

Timing closure tool

シミュレーション

EDA ベンダー 製品名 デザイン・ソリューション

Aldec, Inc.

Active-HDL

Simulation

Riviera-PRO

Simulation

Cadence Design Systems,Inc.

Incisive Enterprise Simulator

Simulation

Mentor Graphics

ModelSim®

Simulation

Questa Advanced Simulator

Simulation

Symphony EDA VHDL Simili

Simulation

SynaptiCAD VeriLogger Extreme

Simulation

Synopsys

VCS

Simulation

検証パートナー

EDA ベンダー 製品名 デザイン・ソリューション
Aldec, Inc. ALINT-PRO

Register transfer level (RTL) checker

Atrenta SpyGlass Lint checks
SpyGlass CDC

Clock domain crossing (CDC) verification

SpyGlass Constraints

Timing constraints verification

Blue Pearl

Analyze RTL

RTL checker

Create Timing Constraints

Constraints generator

Cadence Design Systems,Inc. Encounter Conformal Equivalence Checker

Formal verification

EMA Design Automation TimingDesigner

Timing verification

FishTail

Focus

Constraints generator

Confirm

Timing-exception verification

ReConfirm

Timing-exception validation

Mentor Graphics

FormalPro

Equivalence checking

Questa Formal Verification

Functional verification

Questa Clock-Domain Crossing Verification

Clock domain crossing verification

Real Intent Meridian CDC

Clock domain crossing verification

SynaptiCAD

TestBencher Pro

Testbench generator

WaveFormer Pro

Timing verification

Synopsys

Leda

RTL checker

Magellan

Functional verification

Formality

Formal verification

ProtoLink Probe Visualizer

Integrated RTL debug for FPGA prototype board

Temento Systems

Dialite – Platform Edition

In-system verification and integrated RTL debug

AMBA Bus Verification

In-system verification

TransEDA

VN-Spec

Specification checker

VN-Check

RTL checker

VN-Cover

Finite state machine (FSM) coverage tool

Coverability Analysis

Code coverage tool for simulation and testbench generation

Assertain-HDL

RTL checker for simulation coverage

Assertain-ABV

RTL checker for functional verification coverage

ボードレベル設計パートナー

EDA ベンダー 製品名 デザイン・ソリューション
Agilent Technologies Advanced Design System (ADS)

Signal integrity (SI) analysis

Altium Altium Designer

PCB board schematics and layout
SI analysis

Cadence Design Systems,Inc.

Allegro FPGA System Planner

FPGA I/O planning

OrCAD FPGA System Planner

FPGA I/O planning

Allegro PCB SI

SI analysis

OrCAD Signal Explorer

SI analysis

Allegro Design Authoring
Allegro Design Entry Capture / Capture CIS

PCB board schematics

Cadence OrCAD Capture and Capture CIS

PCB board schematics

Allegro PCB Designer

PCB board layout

OrCAD PCB Designer

PCB board layout

Mentor Graphics

I/O Designer

FPGA I/O planning

HyperLynx Signal Integrity (SI)

SI analysis

DxDesigner

PCB board schematics

PADS

PCB board schematics and layout

Expedition Enterprise

PCB board layout

Board Station

PCB board layout

Signal Integrity Software, Inc. (SiSoft)

Quantum-SI SI analysis
Synopsys HSPICE

SI analysis

Zuken

CR-5000

PCB board schematics and layout

ASIC プロトタイピング・パートナー

EDA ベンダー 製品名 デザイン・ソリューション
Auspy Development Inc. Auspy Partition System II

Multi-chip partitioning system

Synopsys Certify

Multi-chip partitioning system

全EDA パートナー

ACCESS プログラム・パートナー

システム・レベル設計

デザイン設計

シンセシス

シミュレーション

検証

ボードレベル設計

ASIC プロトタイピング

Aldec, Inc.      

Check

Check

   
Agilent Technologies          

Check

 
Agnisys Technology Pvt Ltd

Check

           
Altium

Check

       

Check

 
Atrenta        

Check

   
Auspy Development Inc.            

Check

Blue Pearl        

Check

   
Bluespec

Check

           
Cadence Design Systems,Inc.

Check

   

Check

Check

Check

 
Duolog Technologies

Check

           
EMA Design Automation        

Check

   
FishTail        

Check

   
Impulse Accelerated
Technologies

Check

           
Mentor Graphics Check Check Check Check Check Check  
NEC

Check

           
PDTi Check            
Poseidon Design Systems Check            
Real Intent        

Check

   
Sigasi  

Check

         
Signal Integrity Software, Inc. (SiSoft)           Check  

Symphony EDA

      Check      

SynaptiCAD

Check     Check Check    
Synopsys® Check   Check Check Check Check Check

Temento Systems

        Check    

TransEDA

        Check    
Zuken           Check  

パートナーに参加