PDF ドキュメント

  • Chapter 1. 概要 (ver 4.0, May 2007, 457 KB)

Chapter 1. Introduction (ver 4.2, Jul 2007, 132 KB)

  • (日本語版なし)

Chapter 2. Stratix II Architecture (ver 4.3, May 2007, 1,011 KB)

Chapter 3. Configuration & Testing (ver 4.2, May 2007, 165 KB)

Chapter 4. Hot Socketing & Power-On Reset (ver 3.2, Apr 2006, 102 KB)

  • (日本語版なし)

Chapter 5. DC & Switching Characteristics (ver 4.5, Apr 2011, 2 MB)

Chapter 6. Reference & Ordering Information (ver 2.2, Apr 2011, 150 KB)

Section I. Clock Management

Chapter 1. PLLs in Stratix II and Stratix II GX Devices (ver 4.6, Jul 2009, 634 KB)

Section II. Memory

Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 376 KB)

Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 387 KB)

Section III. I/O Standards

Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices (ver 4.6, Jan 2008, 491 KB)

Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 337 KB)

Section IV. Digital Signal Processing (DSP)

Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices (ver 2.2, Jan 2008, 339 KB)

Section V. Configuration and Remote System Upgrades

Chapter 7. Configuring Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 993 KB)

Chapter 8. Remote System Upgrades with Stratix II and Stratix II GX Devices (ver 4.5, Jan 2008, 291 KB)

Chapter 9. IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix II and Stratix II GX Devices (ver 3.3, Jan 2008, 272 KB)

Section VI. PCB Layout Guidelines

Chapter 10. Package Information for Stratix II & Stratix II GX Devices (ver 4.3, May 2007, 477 KB)

Chapter 11. High-Speed Board Layout Guidelines (ver 1.4, May 2007, 654 KB)

ALTMEMPHY Example

Legacy PHY Example

AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB)

AN 425: Using the Command-Line Jam STAPL Solution for Device Programming (ver 2014.09.22, Sep 2014, 1 MB)Updated

AN 114: Designing with High-Density BGA Packages for Altera Devices (ver 5.3, Sep 2014, 844 KB)Updated

AN 367: Implementing PLL Reconfiguration in Stratix II Devices (ver 2.2, Jul 2012, 628 KB)

Example 1: altpll_reconfig Design with the MIF

Example 2: altpll_reconfig Design with Write Parameters

Example 3: altpll_reconfig Design for Phase Shift Stepping

AN 477: Designing RGMII Interface with FPGA and HardCopy Devices (ver 2.0, Jan 2010, 519 KB)

AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.3, Apr 2009, 784 KB)

Example Design for AN 462: top.qar

AN 327: Interfacing DDR SDRAM with Stratix II Devices (ver 3.2, Sep 2008, 938 KB)

AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.4, Jul 2008, 371 KB)

AN 449: External Memory Interface Design Guidelines for Stratix II, Stratix II GX, and Arria GX Devices (ver 1.2, Sep 2007, 284 KB)

AN 409: Design Example Using the altlvds Megafunction & the External PLL Option in Stratix II Devices (ver 1.0, Mar 2006, 244 KB)

Design Example

AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)

Design Example 1

Design Example 2

User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1)

User-Mode Calibration Reference Design (Quartus II Version 5.0)

Design Files

AN 315: Guidelines for Designing High-Speed FPGA PCBs (ver 1.1, Feb 2004, 2 MB)

Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)

Basic Principles of Signal Integrity (ver 1.3, Dec 2007, 548 KB)

Tcl File

Readme File

Errata Sheets

Technical Briefs

Product Overview

Device Pin-Out Files

Process Change Notifications

Inserts and Advertorials

Application Briefs