Altera is the first company to offer transceiver dynamic reconfiguration to support multiple protocols, data rates and physical medium attachment (PMA) settings.
Dynamic reconfiguration, a feature supported in Stratix® II GX device transceivers, benefit customers in a number of ways, including:
- Providing unprecedented flexibility by enabling transceivers to be dynamically reconfigured for different protocols, data rates and PMA settings without interrupting adjacent transceiver channels
- Dynamically optimizing signal integrity for backplane applications
- Making Plug & Play Signal Integrity possible
Increasing productivity by eliminating in-field system downtime
- Universal front end (UFE) serial interface with flexibility to support multiple protocols (such as SONET, Fibre Channel and Gigabit Ethernet) using the same hardware
- Remote upgrades
- Continuous backplane signal integrity optimization to minimize bit-error ratio (BER)
The exponential adoption of high-speed serial interconnect in recent years has posed new challenges. The data rate of serial protocol and proprietary protocol standards are doubling and quadrupling to keep up with ever increasing bandwidth requirements of today’s applications. At the same time, new serial protocol standards get ratified to address new market requirements not addressed by existing serial protocols.
Designers are faced with the challenge of designing systems that support the newer and faster serial protocols while continuing support for slower legacy ones. Until now, design engineers had no choice but to design with multiple ASSPs and boards to support different protocols and data rates. Dynamic reconfiguration delivers an elegant solution for supporting multiple protocols. Dynamic reconfiguration turns a standard FPGA with embedded transceivers into a "Swiss Army Knife" of high-speed serial protocols.
End customers also benefit by having unprecedented flexibility with a UFE serial interface. Customers no longer have to purchase and stock different hardware to support different protocols, they simply dynamically reconfigure the same serial channel to the protocol of choice. Reconfiguration is performed without interruption to other channels and can be performed remotely. For example a serial port may support 3 different protocols and 7 different rates; 1G, 2G and 4G Fibre Channel; SONET/SDH OC3, OC12 and OC48; and Gigabit Ethernet. Figure 1 illustrates a transceiver block configured to support multiple protocols and rates. Each transceiver channel can dynamically access one of the two clock domains from two phase-locked loops (PLLs). What's more, each PLL can derive it's clock source from multiple sources.
Quartus® II development software simplifies channel reconfiguration by generating memory initialization files (MIFs) for each protocol which is used to change transceiver settings via the dynamic reconfiguration block. Figure 2 depicts how the dynamic reconfiguration block (alt2gxb_reconfig) loads unique MIFs which contain transceiver settings for a given protocol.
Figure 1. Transceiver Supports Multiple Protocols
Figure 2. Dynamic Reconfiguration Block
In backplane applications, where transceivers drive both short and long (up to 50” at 6.375 Gbps) FR4 traces, dynamic reconfiguration provides the means for Plug & Play Signal Integrity.