Automatic Cyclic Redundancy Code Checking Feature on Cyclone III FPGAs

Cyclone® III FPGAs offer on-chip circuitry to automatically check cyclic redundancy code. Some critical applications require periodic cyclic redundancy code checks to ensure continued data integrity in a high-reliability environment.

Checking cyclic redundancy code ensures data integrity and is one of the best techniques for mitigating single event upset (SEU) problems. This Cyclone III feature can be easily implemented for all designs at no extra cost and eliminates the need for complex external logic. A Cyclone III FPGA will compute the cyclic redundancy code during configuration and store it on the device. Dedicated circuitry checks it against an automatically computed cyclic redundancy code. The CRC_error pin reports failure when configuration RAM data is changed unintentionally and makes it easy to trigger re-configuration.

Custom-Built Circuitry and Simple Software Interface

Just one simple click turns on automatic cyclic redundancy code checking in the Quartus® II design software. The dedicated circuitry in Cyclone III FPGAs continually and automatically checks for cyclic redundancy code errors in the configuration SRAM cells while the device is in user mode.

You can monitor an external pin for the error and use it for re-configuration. Clock frequency is changed by modulating the clock divider to select the desired checking period.