About Using the Encounter Conformal Software with the Quartus II Software

You can use the Cadence Encounter Conformal software to perform formal verification of a Synopsys Synplify-generated Verilog Quartus Mapping File (.vqm) and a corresponding post-fit Verilog Output File (.vo) generated by the Quartus II software.

The following topics describe the typical flow to perform formal verification using the Quartus II software and the Encounter Conformal software:

1. Set up the Encounter Conformal working environment

2. Perform formal verification with the Encounter Conformal software

3. Perform formal verification with Quartus II Integrated Synthesis and the Encounter Conformal software

You can also use Quartus II Integrated Synthesis to synthesize a design and then perform an RTL to gate-level equivalence verification using the Encounter Conformal software. The Encounter Conformal software compares the RTL netlist (described in Verilog HDL or VHDL) to the Quartus II-generated gate-level, post-fit Verilog Output File for functional equivalence.

Refer to the Design Guidelines for Using Quartus II Integrated Synthesis and the Encounter Conformal Software topic for design guidelines to avoid mismatches when performing formal verification.