You can use the Synopsys PrimeTime software to perform a timing verification of a Verilog Output File (.vo) after compilation with the Quartus II software. The Quartus II software also generates a Tcl Script File (.tcl), which sets up the PrimeTime environment for performing a timing verification.
The following topics describe the typical flow for to perform a timing verification with the PrimeTime software:
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Note: You can run the PrimeTime software automatically from within the Quartus II software using the NativeLink feature only on Linux workstations. |
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More information is available on other EDA timing tools on the Altera website. |
