Performing a Functional Simulation with the ModelSim Software

1. If you have not already done so, set up a project with the ModelSim software.

2. To map the design libraries to your work library:

   1. On the File menu, point to New and click Library (File menu). The Create a New Library dialog box appears.

   2. Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK.

   3. Repeat steps 2a and 2b to map altera_mf to the work library.

3. To compile the functional simulation libraries, Verilog HDL or VHDL Design Files, and test bench files (if you are using a test bench):

1. 1. On the Compile menu, click Compile.

   2. In the Library list of the Compile HDL Source Files dialog box, select the work library.

   3. In the File name list, type the directory path and file name of the functional simulation libraries.

      or

      In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog HDL or VHDL Design File.

   4. Click Compile.

1. 5. Repeat steps 4b to 4d to compile the Verilog HDL or VHDL Design File.

   6. Repeat steps 4b to 4d to compile the test bench file(s).

   7. Click Done.

4. To load the design:

   1. On the Simulate menu, click Simulate. The Simulate dialog box appears.

   2. In the Name list, click the + icon to expand the work directory.

   3. Select the top-level design file to simulate.

   4. Click Add.

   5. Click Load.

5. Perform the functional simulation in the ModelSim software.

1. If you have not already done so, perform Setting Up a ModelSim Project with Command-Line Commands.

2. To compile the functional simulation libraries, VHDL or Verilog HDL design file, and optional test bench file, type the following commands at the ModelSim prompt:

Map to library work:

vlib lpm
vlib altera
vlib sgate
vmap lpm work
vmap altera work
vmap sgate work

For VHDL 87-compliant designs:

vcom -work work <path to library>/220pack.vhd 
vcom [-87] -explicit -work work <path to library>/220model_87.vhd 
vcom -work work <path to library>/altera_mf_components.vhd 
vcom [-87] -work work <path to library>/altera_mf_87.vhd 
vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

For VHDL 93-compliant designs:

vcom -93 -work work <path to library>/220pack.vhd 
vcom -explicit -work work <path to library>/220model.vhd 
vcom -work work <path to library>/altera_mf_components.vhd 
vcom -93 -work work <path to library>/altera_mf.vhd 
vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

For Verilog HDL designs:

vlog -work work <path to library>/220model.v 
vlog -work work <path to library>/altera_mf.v 
vlog -work work <design name>.v 
vlog -work work <test bench>.v  

3. Load the VHDL or Verilog HDL design file or test bench file for the design into the ModelSim software by typing one of the following commands at the command prompt:

4. vsim <work library>.<design name> 

   or

   vsim <work library>.<top-level design entity> 

5. Perform the functional simulation in the ModelSim software.