To compile the atom simulation model libraries, Verilog Output File (.vo) or VHDL Output File (.vho), and test bench files in the Mentor Graphics ModelSim PE or SE software:
To compile libraries and design files with the ModelSim interface:
-
If you have not already done so, set up a project with the ModelSim software.
-
On the Compile menu click Compile.
-
In the Library list of the Compile HDL Source Files dialog box, select the work library.
-
In the Files of Type list, select All Files (*.*), and in the Look in list, select the appropriate simulation model library.
|
|
Note: For VHDL-93 compliant designs, turn on Use 1993 Language Syntax under Default Options. |
-
Click Compile.
-
Repeat steps 2 to 4 for the Verilog HDL or VHDL Output File and the test bench file (if you are using one) that instantiates the Verilog HDL or VHDL Output File.
|
|
Important: If your design contains the altgxb megafunction or the alt2gxb megafunction, please refer to the appropriate megafunction topic for required settings information. |
-
Click Done.
To compile libraries and design files for a ModelSim project with command-line commands:
-
If you have not already done so, perform set up a ModelSim project with command-line commands.
|
|
Important: If your design contains the altgxb megafunction or the alt2gxb megafunction, please refer to the appropriate megafunction topic for required settings information. |
-
Enter the following commands to direct the ModelSim software to compile the appropriate libraries and design files for VHDL designs.
If your design contains the altgxb or alt2gxb megafunction, type the following commands at the ModelSim prompt:
vlib lpm 
vlib altera
vlib sgate
vmap lpm work
vmap altera work
vmap sgate work
vcom -work lpm <path to library>/220pack.vhd
vcom -work lpm <path to library>/220model.vhd
vcom -work sgate <path to library>/sgate_pack.vhd
vcom -work sgate <path to library>/sgate.vhd
vcom -work stratixiigx_gxb <path to library>/stratixiigx_hssi_atoms.vhd
vcom -work stratixiigx_gxb <path to library>/stratixiigx_hssi_components.vhd
or, for a design targetting a Stratix IV device:
vcom -work stratixivgx_gxb <path to library>/stratixivgx_hssi_atoms.vhd
vcom -work stratixivgx_gxb stratixivgx_hssi_components.vhd
To compile the device-specific simulation models, VHDL Output File, and test bench file (if you are using one), type the following commands at the ModelSim prompt:
vcom -work work <path to library>/altera_primitves.vhd (If your design targets a Stratix III or Cyclone III device.)
vcom -work work <path to library>/altera_primitves_components.vhd (If your design targets a Stratix III or Cyclone III device.)
vcom -work work <path to library>/<device family>_components.vhd
vcom -work work <path to library>/<device family>_atoms.vhd
vcom -work work <design name>.vho
vcom -work work <test bench>.vhd
|
|
Note: For VHDL 93-compliant designs for APEX 20KE devices, type the following command to compile the simulation model:
|
-
Enter the following commands to direct the ModelSim software to compile the appropriate libraries and design files for Verilog HDL designs.
If your design contains the altgxb megafunction, type the following commands at the ModelSim prompt:
vlog -work work <path to library>/220model.v
vlog -work worksgate.v
To compile the device-specific simulation models, Verilog Output File, and test bench file (if you are using one), type the following commands at the ModelSim prompt:
vlog -work work <path to library>/altera_primitives.v <path to library>/<device family>(If your design targets a Stratix III, Stratix IV, or Cyclone III device.)
vlog -work work _atoms.v <test bench>
vlog -work work <design name>.vo
vlog -work work .v
To continue with the ModelSim simulation flow, perform a timing simulation with the ModelSim software.
