Performing a Functional Simulation with the ModelSim-Altera Software

1. If you have not already done so, set up a project with the ModelSim-Altera software.

2. To compile the Verilog HDL or VHDL Design Files and test bench files (if you are using a test bench):

1. On the Compile menu, click Compile.

2. In the Library list of the Compile HDL Source Files dialog box, select the work library.

3. In the File name list, type the directory path and file name of the Verilog HDL or VHDL Design File.

   or

   In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog HDL or VHDL Design File.

4. Click Compile.

5. Repeat steps 2b to 2d to compile the test bench file(s).

6. Click Done.

3. To load the design:

   1. On the Simulate menu, click Simulate. The Simulate dialog box appears.

   2. If you are simulating a Verilog HDL design, to specify the ModelSim precompiled libraries:

      1. Click the Libraries tab.

      2. In the Search Libraries (-L) box, click Add and select the appropriate libraries.

      3. Click OK.

   3. In the Name list, click the + icon to expand the work directory.

   4. Select the top-level design file to simulate.

   5. Click Add.

   6. Click Load.

4. Perform the functional simulation in the ModelSim-Altera software.

To use the Mentor Graphics ModelSim-Altera software, provided with the Quartus II software, to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components using command-line commands:

1. If you have not already done so, set up a ModelSim-Altera project with command-line commands.

2. If your design contains the altgxb megafunction, to map to the precompiled Stratix GX functional simulation model libraries type the following command at the ModelSim prompt:

   vmap altgxb /<ModelSim-Altera install directory>/altera/<verilog or vhdl>/altgxb/ 
    

   Important: If your design contains the altgxb megafunction or the alt2gxb megafunction, please refer to the appropriate megafunction topic for required settings information.

    

3. To map the VHDL-87-compliant design libraries, type the following commands at the ModelSim prompt:

vmap lpm /<ModelSim-Altera install directory>/altera/vhdl/220model_87/ 
vmap altera_mf /<ModelSim-Altera install directory>/altera/altera_mf_87/ 

4. To compile the Verilog HDL or VHDL Design Files and test bench files (if you are using a test bench), type the following commands at the ModelSim prompt.

   For VHDL designs:

   vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

   For Verilog HDL designs:

   vlog -work work <design name>.v 
   vlog -work work <test bench>.v 

5. To load the design, type the following commands at the ModelSim prompt.

   For VHDL designs:

   vsim work.<top-level design entity> 

   For Verilog HDL designs:

   vsim -L altera_mf_ver -L lpm_ver.<top-level design entity> 

6. Perform the functional simulation in the ModelSim-Altera software.