You can perform RTL functional simulation, post-synthesis simulation, and gate-level timing simulation of VHDL or Verilog HDL designs with the Aldec Active-HDL software. The following steps describe procedures for setting up Active_HDL and then performing each type of simulation:
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Set up the Active-HDL working environment with the Active-HDL software
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Perform a simulation of a Verilog HDL design with the Active-HDL software
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Perform a simulation of a VHDL design with the Active-HDL software
