Generating Output Files for Board-Level Tools

Altera's Quartus^® II software interfaces with industry-standard EDA board-level tools. For more information about how to specify a board-level symbol integration, signal integrity, or timing analysis tool and/or corresponding output file with the Quartus II software design flow, choose a board-level tool from this list:

• Generate Board-Level Timing Analysis Files
  • Mentor Graphics TAU
• Generate Board-Level Symbol Output Files
  • Mentor Graphics^® I/O Designer FPGA Xchange-Format Files
  • Mentor Graphics DxParts PartMiner edaXML-Format Files
• Generate Board-Level Signal Integrity Analysis Files
  • HSPICE Simulation Deck Files
  • IBIS Output Files
• Generate Boundary-Scan Description Language Files
  • BSDL Files