10-Gbps Ethernet Loopback Reference Design

from Altera

Overview

Altera's 10-Gbps Ethernet Loopback reference design provides a quick way to implement your own 10-Gigabit Ethernet (10 GbE)-based design in an Altera^® FPGA, and observe live network traffic flowing through a loopback Ethernet optical multimode cable assembly. This design also helps you to verify your 10 GbE-based system operation with an Altera 10-GbE media access controller (MAC) function and a standard off-the-shelf 10-GbE physical medium dependent (PMD) device. The Altera 10-GbE MAC is validated by the University of New Hampshire Interoperability Lab (UNH-IOL). You can leverage this reference design to build your own 10-GbE system with low risk and minimal effort.

The reference design is built with Altera's SOPC Builder using two instances of the Altera 10-GbE Reference Design function in a Stratix^® II GX FPGA and eight of the 3.125-Gbit serial transceivers in the FPGA to implement two 10-GbE XAUI ports. This reference design demonstrates the operation of the 10-GbE function up to the maximum wire-speed performance in a 2-port loopback hardware configuration.

Features

• Showcases two instances of the Altera 10-GbE reference design function supporting 10-Gbps Ethernet operations in XAUI mode
• Demonstrates sending, receiving, and automatic checking of Ethernet frames up to the maximum theoretical data rate at the wire
• Jump-starts your embedded system design/performance evaluation
  • Minimal hardware requirements: Stratix II GX PCI Express development kit upgraded with an EP2SGX130 F1508 packaged device, two high-speed mezzanine connectors (HSMC) to x2 adapter cards and two optical x2 modules, Ethernet multi-mode fiber loopback cable assembly, a host computer, and an Altera USB-Blaster^TM or ByteBlaster^TM cable assembly
  • Programmable settings include number of frames, frame length, and payload data type
  • Step-by-step walk-through instructions, complete design files (including Quartus^® II archive), and Windows XP-based software application for test control and monitoring are provided

Demonstrated Altera Technology

• Stratix II GX FPGAs
• Altera 10-Gbps Ethernet Reference Design function
• Nios^® II embedded processor intellectual property (IP) cores
• Altera CRC Compiler Megacore^® function
• Nios II Embedded Design Suite (EDS)
• SOPC Builder
• Avalon^® system interconnect

Block Diagram

Figure 1. 10-Gbps Ethernet Loopback Reference Design (1)

Note:

1. This reference design runs on a modified Stratix II GX PCI Express development board upgraded with a EP2SGX130 FPGA. This special 10-GbE Loopback Reference Design hardware setup can be obtained by contacting your local Altera sales representative.

Related Links

• Stratix II GX FPGAs
• Altera 10-Gbps Ethernet XAUI solution
• Altera 10-Gbps Ethernet Reference Design function
• Altera Nios II MegaCore Function
• Altera CRC Compiler Megacore function
• Altera Nios II EDS
• Altera SOPC Builder
• PCI Express Development Kit, Stratix II GX Edition
• AN 561: Stratix II GX 10GbE Loopback Reference Design (PDF)
• AN 516: 10-Gbps Ethernet Reference Design (PDF)
• AN 440: Accelerating Nios II Networking Applications (PDF)

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.