ソリューション ID: rd07092004_5865
掲載日: 2007年5月18日
製品カテゴリー: IP (Intellectual Property)
製品エリア: IP その他
製品サブ・エリア: その他(IP)
デバイス・ファミリ: STRATIX,STRATIX GX,STRATIX II
IP 製品: POSPHY Level 4 (SPI 4.2)

件名

What are the pin constraints when using the POS-PHY Level 4 Core v2.2.0 or v2.2.1 with Stratix®, Stratix GX, or Stratix II devices?

回答

The POS-PHY Level 4 Core does not have any pin constraints other than those required by the I/O standard you are using. The following is a summary of the requirements:

• tdclk should be placed on an output data pin to match the data output propagation delay.
• For static alignment, the transmitter outputs should be place in the same I/O bank.
• Quartus^® II imposes limitations on placing single ended pins adjacent to differential pairs to have better noise immunity. The specific limitations are built into Quartus II and will vary based on package and device. Device migration in the same package effects different pins since they are wire bonded differently.

Stratix II:

64-bit / 128-bit cores:

• High speed Data / Control (LVDS): I/O banks 1,2,5,6. All high-speed pins for a single receiver must be in the same I/O bank.
• Status bus (LVTTL): Any I/O banks, subject to normal bank assignment rules.
• Note: LVTTL Outputs (such as the status bus for the receiver core) require 3.3 V reference voltage, but Stratix II LVDS requires a 2.5 V reference voltage. This means that the POS-PHY Level 4 core's status outputs cannot be on the same I/O bank as its data inputs. This is not a problem with Stratix because the LVDS reference voltage is 3.3 V.

32-bit cores:

• High speed Data / Control (LVTTL): Any I/O banks, subject to normal bank assignment rules.
• Status bus (LVTTL): Any I/O banks, subject to normal bank assignment rules.

Stratix / Stratix GX:

64-bit / 128-bit cores:

• High speed Data / Control (LVDS): I/O banks 1 and 2 only
• Status bus (LVTTL): Any I/O banks, subject to normal bank assignment rules.

32-bit cores:

• High speed Data / Control (LVTTL): Any I/O banks, subject to normal bank assignment rules.
• Status bus (LVTTL): Any I/O banks, subject to normal bank assignment rules.

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