This section lists any issues related to the example designs included with the Nios® II Development Kit.
Low-Cost Example Design Does Not Boot From EPCS 
Boot from EPCS fails if you are using the low_cost example design hardware image installed with the Nios II Development Kit version 5.0.
Workaround: Open the low_cost project in Quartus® II software and re-compile the design. The new SOF file will successfully boot from EPCS. No SOPC re-generation or software recompilation is necessary.
Cyclone II EP2C35 example designs from Nios II version 5.0 Customer Beta may not function on production Nios II Development Boards, Cyclone II Edition
The Nios II development kit, CycloneTM II Edition examples are compiled for an EP2C35F672C6, which is a -6 speed grade device. While the designs are compiled for this -6 speed grade device, most of the Rev0 Cyclone II Nios II boards in circulation contain a slower -8 speed grade device. This can cause some of the example designs to fail on those boards. The final production boards, Rev01, contain a -6 device.
In addition to upgrading to -6 devices, the production boards will also resolve an issue with the RAS and CAS pins of the DDR SDRAM. On the Rev0 board, the traces for these pins were accidentally swapped. In Nios II 5.0 Customer Beta, RC1, and RC2, this is corrected by re-swapping them in the Cyclone II example design top-level BDF files. On the production boards, the board traces will be corrected, and the final release of Nios II 5.0 will reflect this by removing the re-swapping in the Cyclone II example designs. The impact of this is that for the final release of Nios II 5.0, Cyclone II example designs using DDR SDRAM will NOT work on Rev0 Cyclone II Nios boards.
Please do the following to ensure reliable example design operation if you are using a Rev0 Cyclone II Nios board (EP2C35F672C8) with the example designs:
- Change the device assignment in Quartus II software for the Cyclone II example design projects to EP2C35F672C8, and recompile to make sure the design meets timing before running the design.
- Swap the RAS and CAS pins for the DDR SDRAM in the top level BDF file.
If you are using Nios II version 5.0 release example designs with production Cyclone II Nios board (EP2C35F672C6), everything should work out-of-the-box and no modifications to the example designs will be necessary.
"Error While Loading IP Toolbench" when editing DDR component in Cyclone II example designs
You may get this error if you are using example designs from Nios II version 5.0 Customer Beta and are attempting to edit the DDR Controller intellectual property (IP).
Workaround: Delete the old DDR Controller component from the SOPC Builder system installed with the Customer Beta and re-add the DDR Controller that is installed with the release version of the MegaCore® IP Library 5.0.
