Altera provides extensive documentation and support for the POS-PHY Level 4 MegaCore® function to help you quickly and easily develop and debug POS-PHY Level 4 (SPI-4.2) applications.
Literature
- POS-PHY Level 4 MegaCore Function User Guide (PDF)
- Altera Atlantic Specification (PDF)
- MegaCore IP Library Release Notes and Errata (PDF)
- Archive of Intellectual Property Release Notes
- Archive of Intellectual Property Errata Sheets
Application Notes
Reference Designs
Design Examples
Altera Knowledge Database
The Knowledge Database provides support solutions, answers to frequently asked questions, and information about known issues regarding the POS-PHY Level 4 MegaCore function.
See frequently viewed solutions:
- Are there any known issues with POS PHY Level 4 (SPI-4.2) Transmitter FIFO Threshold High(FTH) value in the User Guide?
- Why doesn't the Altera SPI-4.2 Atlantic FIFO size parameter indicate actual usable bytes of the FIFO?
- Can PLLs for TX and RX be shared using the SPI-4.2 core in Stratix IV GX ES devices?
- Why does aN_atxdav de-assert when the SPI-4.2 data path receiver is reset?
- What are the pin constraints when using the POS-PHY Level 4 Core v2.2.0 or v2.2.1 with Stratix, Stratix GX, or Stratix II devices?
Find additional solutions on the POS-PHY Level 4 MegaCore function.
Development Kits
The following development kits are available for the POS-PHY Level 4 MegaCore function:
- Cyclone® III Starter FPGA Kit
- PCI Express Development Kit, Stratix II GX Edition
- Stratix III FPGA Development Kit
- Stratix IV GX FPGA Development Kit
