This example describes an 8-bit signed multiplier-accumulator design with registered I/O ports and a synchronous load input in VHDL. Synthesis tools are able to detect multiplier-accumulator designs in the HDL code and automatically infer the altmult_accum megafunction or map the logic to DSP blocks in the target device architecture.
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Table 1 lists the ports in the signed multiplier-accumulator design.
| Table 1. Signed Multiplier-Accumulator Port Listing | ||
| Port Name | Type | Description |
a[7:0], b[7:0] |
Input | 8-bit registered data inputs |
clk |
Input | Clock input |
| sload | Input | Synchronous load input |
accum_out[15:0] |
Output | 16-bit output |
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