In a polyphase interpolation filter the output sample rate is n times the input sample rate, with n being the interpolation factor. Polyphase filters can simplify the overall design and reduce the number of computations needed. This document describes the implementation of a 16-tap low-pass finite impulse response (FIR) filter using four polyphase interpolation filter banks.
A single DSP block can implement up to four taps. By cycling the coefficients on every cycle of the 4x clock, it can implement the 16-tap FIR filter. The coefficient-loading schedule is shown in Table 1. Input samples and data are loaded in parallel and can be up to 18 bits wide.
| Table 1. Coefficient-Loading Schedule for Interpolation Polyphase Filter | |
| Cycle of 4x Clock | Coefficients to be Loaded |
| 1, 5…… | h(0), h(4), h(8), h(12) |
| 2, 6…… | h(1), h(5), h(9), h(13) |
| 3, 7…… | h(2), h(6), h(10), h(14) |
| 4, 8…… | h(3), h(7), h(11), h(15) |
For more details, see the Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook.
Download the files used in this example:
- Download interpolation_FIR.zip
- Download Polyphase Interpolation FIR Filter Design Example README File
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Files in the download include:
- inter_poly.v - Top-level design file
- pll.v - Phase-locked loop (PLL) to generate 1x and 4x clock
- mult_add.v - Multiply-add function implemented using altmult_add megafunction
- rom0.v, rom1.v, rom2.v, rom3.v - ROM blocks to store filter coefficients
- rom1.mif, rom1.mif, rom2.mif, rom3.mif - Memory initialization file for filter coefficients
- inter_poly.m - MATLAB script to verify functionality of design
Figure 1 illustrates the inter_poly top-level block diagram.
Figure 1. inter_poly Top- Level Block Diagram
Table 2 contains the polyphase interpolation FIR filter design example port listing.
| Table 2. Polyphase Interpolation FIR Filter Design Example Port Listing | ||
| Port Name | Type | Description |
| x0[17..0] | Input | Signed 18-bit input data is shifted in serially using the shift register within the DSP block |
| clk | Input | Clock |
| clken | Input | Clock enable |
| reset | Input | Reset |
| load_data | Output | When asserted, the filter is ready to accept data on the x0 port |
| result[25..0] | Output | Output of the interpolation FIR filter |
For more information on using this example, go to:
- How to Use Verilog HDL Examples
- Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook
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