This design demonstrates a Stratix® IV device interfacing with a 18-bit wide QDR II+ SRAM component and a 36-bit RLDRAM II component running at 400 MHz. This implementation requires device resource sharing such as delay-locked loops (DLLs), phase-locked loops (PLLs), and on-chip termination (OCT) and requires extra steps to create the interfaces in a Quartus II design project.
The design features advanced I/O timing, board trace models, and the SignalTapTM II logic analyzer in Quartus® II software. It is mapped to the Stratix IV E FPGA Development Kit.
A walkthrough of the process is described in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the Implementing Multiple Memory Interfaces Using UniPHY chapter for the full design guidelines and flow.
This design includes Tcl files for:
- Board trace models for the Stratix IV E FPGA Development Kit example driver "output ports" virtual pin assignments
- Pin location assignments for Stratix IV E FPGA Development Kit QDR II+ SRAM and RLDRAM II Interface
Download the files used in this example:
- Download emi_multiple_rldramii_qdrii_plus_siv_readme.txt
- Download emi_multiple_rldramii_qdrii_plus_siv.zip
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