This design demonstrates DDR3 SDRAM at 400 MHz with Qsys integrated in a Stratix IV GX Audio Video Development Kit board.
The design features advanced I/O timing, board trace models, an example Nios® II test program (DDR_TEST.c). and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to the Stratix IV GX Development Kit.
This design provides a walkthrough of the process presented in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the DDR3 SDRAM Controller with UniPHY Using Qsys chapter for the full design guidelines and flow.
Download the files used in this example:
- Download emi_uniphy_ddr3_siv_qsys_readme.txt
- Download emi_uniphy_ddr3_siv_qsys.zip
Related Links
- Stratix IV GX Audio Video Development Kit
- Volume 6, Section II of the External Memory Interface Handbook (PDF)
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
