Verilog HDL: Four DDR3 ALTMEMPHY-Based Controllers
for Stratix IV FPGAs

This design shows how four DIMMs fit in one FPGA. It also shows how to replace four exact controllers with one ALTMEMPHY instantiation in a Stratix^® IV FPGA.

This design shows four x72 DDR3 SDRAM DIMM high-performance controllers fitting in a EP4SGX530 F1932 device. No resources were shared in this design.

The synopsis design constraint (SDC) and report_timing.tcl files constrain and report the timing result for all four controllers without additional work.

This design was never simulated or tested on the board.

Download the files used in this example:

• Download 4ddr3_readme.txt
• Download 4ddr3_example.zip

Design examples disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.