Verilog HDL: Interfacing 350-MHz QDR II+ SRAM in a Stratix IV FPGA

This design demonstrates a Stratix^® IV device interfacing with 18-bit wide QDR II+ SRAM running at 350 MHz.

The design features advanced I/O timing, board trace models, and the SignalTap^® II logic analyzer in Quartus^® II software. It is mapped to the Stratix IV GX Development Kit.

A walkthrough of the process is described in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the Using QDR II and QDR II+ SRAM in Arria II, Stratix III, and Stratix IV Devices chapter for the full design guidelines and flow.

This design includes Tcl files for:

• Example driver "output ports" virtual pin assignments
• Pin location assignments for the Stratix IV GX Development Kit QDR II+ SRAM Interface

Download the files used in this example:

• Download emi_qdrii_plus_siv_readme.txt
• Download emi_qdrii_plus_siv.zip

Related Links

• Stratix IV GX Development Kit
• Volume 6, Section II of the External Memory Interface Handbook (PDF)

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