Verilog HDL: 72-Bit Wide DDR2 SDRAM ALTMEMPHY-Based Interface
for Stratix III FPGAs

This design demonstrates a Stratix^® III device interfacing with 72-bit wide DDR2 SDRAM UDIMM running at 400 MHz.

The design features advanced I/O timing, board trace models, and the SignalTap^® II logic analyzer in Quartus^® II software. It is mapped to the Stratix III FPGA Development Kit.

A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook. Please refer to the Using DDR and DDR2 SDRAM in Stratix III and Stratix IV devices chapter for the full design guidelines and flow.

Download the files used in this example:

• Download emi_ddr2_siii_readme.txt
• Download emi_ddr2_siii.zip

Related Links

• Stratix III FPGA Development Kit
• Volume 6, Section I of the External Memory Interface Handbook

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