This design demonstrates a Stratix® III device interfacing with 72-bit wide DDR3 SDRAM UDIMM running at 533 MHz.
The design features advanced I/O timing, board trace models, and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to an Altera® internal board.
A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook (PDF). Please refer to the Using DDR3 SDRAM in Stratix III and Stratix IV devices chapter for the full design guidelines and flow.
This design includes Tcl files for:
- Board trace models for the Altera internal board
- Example driver output ports virtual pin assignments
- Pin location assignments for the Stratix III memory board (internal board) DDR3 SDRAM UDIMM Interface
Download the files used in this example:
- Download emi_ddr3_siii_readme.txt
- Download emi_ddr3_siii.zip
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Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
