This design demonstrates a Stratix® III device interfacing with 36-bit wide RLDRAM II running at 400 MHz.
The design features advanced I/O timing, board trace models, and the SignalTap® II logic analyzer in Quartus® II software. It is mapped to an internal board
A walkthrough of the process is described in Volume 6, Section II of the External Memory Interface Handbook (PDF). Please refer to the Using RLDRAM II in Stratix III, and Stratix IV Devices chapter for the full design guidelines and flow.
Download the files used in this example:
- Download emi_rlii_siii_readme.txt
- Download emi_rlii_siii.zip
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These design examples may only be used within Altera® devices and remain the property of Altera Corporation. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
