This design demonstrates an ALTMEMPHY-based QDRII+ interface at 400 MHz, x18-bit wide, and half rate, mapped to the Stratix® III-F1152 Development Host Kit Board. The design writes to 100 addresses in QDRII memory and then reads the data back. The read back data is compared with the data written and the pass or fail signal is asserted accordingly.
This design provides a walk-through of the process presented in AN 461: Design Guidelines for Implementing QDRII and QDRII+ SRAM Interfaces in Stratix III and Stratix IV Devices (PDF). Refer to that document for the full design guidelines and flow.
Download the files used in this example:
- Download an461_readme.txt
- Download an461_example.zip
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