This example demonstrates a native interface design using the High-Performance DDR2 SDRAM Controller II in a Stratix® II device. Timing was closed and simulation was successful.
This design example uses the ALTMEMPHY megafunction-based DDR2 SDRAM High-Performance Controller II MegaCore® function. You can use this design as a timing-closed ALTMEMPHY example.
A walkthrough of the process is described in Volume 6, Section I of the External Memory Interface Handbook (PDF). Please refer to the Using High-Performance Controller II with Native Interface Design chapter for the full design guidelines and flow.
Download the files used in this example:
- Download native_to_avalon_adaptor_readme.txt
- Download native_to_avalon_adaptor.zip
Design examples disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
