This design example is targeted to a Stratix® II GX FPGA and uses the legacy 72-bit wide DDR2 PHY at 267 MHz in full rate mode.
This design includes functional simulation performed using the actual memory device model and can be used as a DDR2 legacy PHY timing-closed example.
This design uses the pin-outs for the PCI Express Development Kit, but was never tested on the board.
This design provides a walk-through of the process presented in AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF). Refer to that document for the full design guidelines and flow.
Download the files used in this example:
- Download an328_legacy_phy_readme.txt
- Download an328_legacy_phy_example.zip
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Design examples disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
