Verilog HDL: 72-Bit Wide DDR2 ALTMEMPHY-Based Interface
for Stratix II FPGAs

This design features a 72-bit wide (five discrete components), 333-MHz /667-Mbps, half-rate DDR2 SDRAM memory interface targeted for the Stratix^® II GX PCI Express Development Board.

This example design uses the ALTMEMPHY megafunction-based DDR2 SDRAM High Performance Controller MegaCore^TM function. You can use this design as a timing-closed ALTMEMPHY example and for board level demonstration.

This design example was generated using the example walk-through described in AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF). Refer to that document for the full design guidelines and flow.

Download the files used in this example:

• Download an328_altmemphy_readme.txt
• Download an328_altmemphy_example.zip

Related links

• AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF)

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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.