Verilog HDL: Three DDR2 ALTMEMPHY-Based Controllers
for Stratix II FPGAs

This design demonstrates three high-performance DDR2 SDRAM controllers in a Stratix^® II device. Timing was closed and simulation was successful.

This design uses the pin-outs for the PCI Express Development Kit, but was never tested on the board.

This design provides a walkthrough of the process presented in AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF). Refer to this document for the full design guidelines and flow.

Download the files used in this example:

• Download an328_stratix-ii-ddr2-multiple-altmemphy_readme.txt
• Download an328_stratix-ii-ddr2-multiple-altmemphy.zip

Related Links

• AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF)

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These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.