This design demonstrates a x32 read and x32 write DDR2 SDRAM interface in Cyclone® III FPGAs. It uses the DDR and DDR2 SDRAM High-Performance Controller MegaCore® function in half rate at 167 MHz targeted to the Cyclone III FPGA Development Kit.
This design includes functional simulation and features the SignalTap® II logic analyzer. This design contains Tcl files for I/O standard settings for all memory interface pins and output enable group assignments, ensuring that VREF rules are met when the design uses input and/or bidirectional pins. It also includes a Tcl file to generate a detailed timing report for all timing paths in the design.
This design provides a walkthrough of the process presented in Volume 6, Section I of the External Memory Interface Handbook. Please refer to the Using DDR and DDR2 SDRAM in Cyclone III Devices chapter for the full design guidelines and flow.
Download the files used in this example:
- Download emi_ddr2_ciii_readme.txt
- Download emi_ddr2_ciii.zip
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