You can use this design example to learn how to perform gate-level timing simulations of your design implemented in a Stratix® II device with the Synopsys VCS simulator.
The Verilog design example contains the post-fit netlist (multiplier.vo) and SDF output data (multiplier_v.sdo) of a sample design obtained after compiling the design with Quartus® II software. The sample design consists of a top-level module (multiplier block) and a simple testbench, test_multiplier.v, that instantiates the design under test (multiplier) and generates the stimulus for running the simulation. The Stratix II device atom libraries required for gate-level simulation are also provided with the example. All functional libraries and device atom libraries come with the Quartus II software. A script, run_vcs, is provided to compile the libraries, netlist file, testbench file, and to run the simulation.
Note: This example was developed using Quartus II software version 9.1 running on a Linux machine and Synopsys VCS version X-2005.06-SP1 running on the same host.
Download the vcs_example.zip design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using This Design Example
Follow these steps to use the design example.
- Restore the vcs_example.qar by double clicking the file after it is saved in the desired location. An alternative method is invoke the Quartus II software.
- Go to Project and select Restore Archived Project.
- In the Archive file name box, type the file name of the vcs_example.qar file or click Browse to select the above .qar file.
- In the Destination folder box, specify the directory path in which you will restore the contents of the file, or browse to a directory that you wish to save.
- Using an Xterm or a console window, at the <sim_prj_loc> directory, source the script run_vcs by typing
%source run_vcs. The script contains commands for the VCS simulator to compile the testbench and the netlist multiplier.vo, annotate the SDF data, and run the simulation for the specified time. If you are using the -RI option in the script, the GUI of VCS is invoked. - In the VCS GUI, click Start Simulation.
The expected and actual results are checked in the testbench, and messages that show whether or not the results match are displayed in the simulator's console window.
For more information on using the Synopsys VCS simulator, refer to the Synopsys VCS User Guide. You can also find detailed information on Synopsys VCS in the Synopsys VCS Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
