This design example demonstrates the use of multiple Nios® II CPUs in an Altera® FPGA. Although this example is primarily aimed at demonstrating a properly constructed hardware system, it also contains the software to exercise the inter-processor communication capabilities of the system.
The hardware portion of this example is created using the SOPC Builder and contains two Nios II CPUs. Each CPU has its own vector interrupt controller (VIC) and timer, but share a DDR SDRAM, a CFI Flash and an on-chip RAM (named the message_buffer_ram). The CPUs are configured to run an application code from its own section in the DDR SDRAM, but data in the on-chip RAM can be shared between the CPUs using the Mailbox and Mutex components. The Mailbox and Mutex components are hardware peripherals that help the CPUs coordinate access to shared peripherals and memory without the danger of corrupting each other's written data.
The software for CPU 1 runs a TCP/IP stack and accepts commands to adjust the frequency of a blinking LED through a telnet connection. CPU 1 uses the Mailbox component of the hardware portion to pass messages regarding the blinking frequency change of the LED to CPU 2. The software for CPU 2 then uses the Mailbox component of the hardware portion to read the messages and adjusts the blinking frequency of the LED accordingly. CPU 2 will continually check the Mailbox component for any new messages and, if there is one, adjusts the blinking frequency of the LED accordingly.
Hardware Design Specifications
- Board support
- Nios II Embedded Evaluation Kit board
- Nios II/f CPU core, debug-enabled, 4 Kbytes I-cache: 2
- Vectored Interrupt Controller (VIC): 2
- System timer: 2
- High resolution timer peripheral: 1
- On-chip RAM (message_buffer_ram): 4 Kbyte
- On-chip RAM (descriptor_memory): 4 Kbyte
- Common Flash Interface (CFI) flash memory interface: 16 Mbytes
- DDR SDRAM controller: 32 Mbytes
- JTAG UART: 1
- RS232 UART: 1
- Performance Counter: 1
- Button PIO peripheral: 1
- EEPROM PIOs: 2
- Triple Speed Ethernet: 1
- Scatter-Gather DMA controllers: 2
- LED PIO peripheral: 1
- Mailbox peripheral: 1
- Mutex peripheral: 1
- System ID peripheral: 1
- Phase-locked loop (PLL) (within the DDR controller): 1
This design example is based on the system constructed in the Nios II Multiprocessor Tutorial (PDF). For detailed information about implementing Nios II multiprocessor systems, refer to the tutorial mentioned above.
Block Diagram
Figure 1. Nios II Multiprocessor System Block Diagram
Download the file used in this example:
The .zip file contains all the necessary hardware and software files to reproduce this example, as well as a readme.txt file.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Related Links
- Creating Multiprocessor Nios II Systems Tutorial (PDF)
- Multiprocessor Coordination Peripherals (PDF)
- Nios II Literature
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
