The templates provided contain Avalon® Memory-Mapped (MM) Verilog modules bundled as an SOPC Builder-ready component. The component is capable of accessing memory and exposes a simple interface you can access with your own custom logic. The component is parameterizable, allowing you to trade off functionality for area and performance optimizations. You can use the components with any Altera® device family supported by SOPC Builder. The component is Verilog based, so you can add your own custom logic to create a self-contained component. Simply use the component editor available in SOPC Builder to create a new component based on the master template Verilog file and your own source file(s). For ease of use, the component uses Tcl callbacks to allow you to make setting changes automatically in a GUI environment.
The system interconnect fabric supports bursting and non-bursting transfers, so various specialized components are provided. Select the component settings that are most appropriate for the memory types in your system to avoid generating excessive logic. Table 1 outlines which component to use, based on your system requirements.
| Table 1. Component Types | |
| Component Type | Typical Usage |
|---|---|
| Burst Read | Bursting SDR/DDR SDRAM, QDR SRAM, RLDRAM, PCIe, PCI, SRIO |
| Pipelined Read | Non-bursting SDR/DDR SDRAM, SSRAM, SRAM, on-chip memory |
| Burst Write | Bursting SDR/DDR SDRAM, QDR SRAM, RLDRAM, PCIe, PCI, SRIO |
| Simple Write | Non-bursting SDR/DDR SDRAM, SSRAM, SRAM, on-chip memory |
The component exposes control and data interfaces for you to connect to your custom logic (see Figure 1). Use the control interface to specify information such as memory addresses, transfer lengths, and handshaking signals. The data interface provides data to or from the master internal buffer using a simple send and acknowledge protocol.
Figure 1. Component Block Diagram
Both the read and write masters share the same interface types and signals. The only exception is that the burst masters require an additional burst count signal. This burst count signal notifies the system interconnect fabric and the memory how many sequential accesses will be made. Altera recommends that you configure the burst master components to use a maximum burst length equal to the maximum burst length of the memory in your system. To learn more about recommended design practices, refer to the Embedded Design Handbook (PDF).
Using This Design Example
Download the Avalon-MM Master Templates (.zip file).
Download the Avalon-MM Master Templates README (.txt file).
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
The .zip file contains all the necessary hardware files to reproduce the example, as well as an Avalon_MM_Masters_Readme.pdf file. The Avalon_MM_Masters_Readme.pdf file contains detailed information about using the templates in your own design.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
