This design example shows the simulation flow between the Mentor Graphics® ModelSim® SE/PE software and the Quartus® II software. With this design example, you can learn how to perform gate-level timing simulations of your design implemented in Stratix® II devices with the Mentor Graphics ModelSim SE/PE simulator.
In this example you will:
- Load an existing project in the Quartus II software
- Set up a Quartus II project to generate the required files for simulation
- Compile your design in the Quartus II software to generate a gate-level netlist
- Understand the outputs generated for gate-level timing simulation
- Run the simulation with the scripts provided and understand the results
The design is created in Verilog HDL and consists of a top-level module (multiplier block), a phase-locked loop (PLL) megafunction, an alt_mult megafunction, an lpm_ram megafunction, and a testbench. The device libraries required for this simulation example come with the Quartus II software. The script provided with this example compiles the required device library files from the Quartus II software installation location.
Note: This example was developed using Quartus II software version 9.0 SP2 running on a Windows XP SP2 machine and Mentor Graphics ModelSim SE software version 6.4a running on the same host.
Download the multiplier_verilog_SE.qar design example.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Using This Design Example
- Invoke the Quartus II software.
- Go to Project, select Restore Archived Project.
- In the Archive file name box, type the file name of the multiplier_verilog_SE.qar file or click Browse to select the above .qar file.
- In the Destination folder box, specify the directory path in which you will restore the contents of the file, or browse to a directory that you wish to save.
Note: You can also double click on the .qar file, the Quartus II software will open and do the archive file process automatically. - On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named multiplier.vo (for use with the ModelSim SE/PE simulator tool) in <project_dir>/simulation/modelsim. The SDF Output File (multiplier_v.sdo) for annotating the delays in the gate-level timing simulation file is also generated at the same location.
To run simulation, use one of the following methods:
Method 1: Running the Quartus II NativeLink Software
Go to the Tools menu, under EDA Simulation Tool, click Run EDA Gate Level Simulation.
Note: For more information, please go to the How to use Quartus II NativeLink web page 9shows you the setting for the NativeLink feature).
Method 2: Running the Modelsim SE/PE Software
- Invoke the Modelsim SE/AE software.
- Go to File menu, select the change directory name to <project_dir>/simulation/modelsim.
Run the multiplier_run_msim_gate_verilog script provided by this design example. To run this script, type do multiplier_run_msim_gate_verilog.do at the command line, then press Enter.
Note: For more information about how to manually perform simulation, please go to the Quick Step on how to manually run simulation web page.
The ModelSim SE/PE simulator compiles the testbench and the netlist (multiplier.vo), annotates the SDF data (in multiplier_v.sdo), and runs the simulation for the specified time. A waveform window within the ModelSim SE/PE simulator is invoked that shows the expected and actual results of the multiplier. The expected and actual results are also checked in the testbench, and messages that show whether or not the results match are displayed in the simulator’s console window. The data output of the multiplier module changes with a delay after the clock edge because the SDF data is annotated in the gate-level timing simulation.
For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook.
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
