Stratix II GX Post-Fit Timing Simulation Design Example with ModelSim SE/PE (Verilog HDL)

This Verilog HDL design example shows the simulation flow between the Mentor Graphics^® ModelSim^® SE/PE software and the Quartus^® II design software. With this design example, you can learn how to perform gate-level timing simulations of your design implemented in Altera^® Stratix^® II GX devices with the Mentor Graphics ModelSim SE/PE simulator.

The design is created in Verilog HDL and consists of a top-level module (multiplier block), an altpll megafunction, an lpm_mult megafunction, an altsynram megafunction, an alt2xgxb megafunction and a testbench. The results of the multiplier are stored in the RAM and then later sent out through the GX transceiver and looped back to its own receiver.

Note: This example was developed using Quartus II software version 9.0 SP2 running on a Windows XP SP2 machine and Mentor Graphics ModelSim SE software version 6.4a running on the same host.

Download the alt2gxb_example_verilog_SE.qar design example.

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Using This Design Example

1. Invoke the Quartus II software.
2. Go to Project, select Restore Archived Project.
3. In the Archive file name box, type the file name of the altgxb_example_verilog_SE.qar file or click Browse to select the above .qar file.
4. In the Destination folder box, specify the directory path in which you will restore the contents of the file, or browse to a directory that you wish to save.
   Note: You can also double click on the .qar file and the Quartus II software will automatically open and perform the archive file process.
5. On the Quartus II software toolbar, click compile. After compilation, the Quartus II software generates a post-fit netlist named alt2gxb_example.vo (for use with the ModelSim SE/PE simulator tool) in <project_dir>/simulation/modelsim. The SDF Output File (alt2gxb_example .sdo), for annotating the delays in the gate-level timing simulation file, is also generated at the same location.

To run simulation, use one of the following methods:

Method 1: Running the Quartus II NativeLink Software

Go to the Tools menu, under EDA Simulation Tool, click Run EDA Gate Level Simulation.

Note: For more information, please go to How to use Quartus II NativeLink Feature web page (shows you the setting for the NativeLink feature).

Method 2: Running the ModelSim SE/PE Software

1. Invoke the software Modelsim SE/AE.
2. Go to File menu, select the change directory name to <project_dir>/simulation/modelsim.
3. Run the alt2gxb_example_run_msim_gate_verilog script provided by this design example. To run this script, type do alt2gxb_example_run_msim_gate_verilog.do in the Transcript window, then press Enter.

Note: For more information about how to manually perform simulation, please go to the Quick Step on how to manually run simulation web page.

For more information on using the Mentor Graphics ModelSim simulator tool, refer to Mentor Graphics ModelSim software documentation and the Mentor Graphics ModelSim Support (PDF) chapter in volume 3 of the Quartus II Development Software Handbook (PDF).

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.