You can perform active parallel (AP) configuration using a supported parallel flash memory. During AP configuration, the Altera® device is the master and the parallel flash memory is the slave. Configuration data is transferred to the Altera device on the
DATA[15:0] pins. This configuration data is synchronized to the
DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Altera device during AP configuration is approximately 40 MHz.
For more information, please refer to the configuration chapter of the of the relevant Altera device in the Configuration Handbook.
- AN 478: Using FPGA-Based Parallel Flash Loader with the Quartus II Software (PDF)—Method to use the FPGA's JTAG interface to perform in-system programming for the parallel flash memory device.