Arria GX Device Configuration

Arria^® GX FPGAs support the following configuration schemes:

Serial—Used to conserve pins
- Active Serial (AS)
  - Uses the Arria GX FPGA to control the configuration process and get the configuration data from a serial configuraton (EPCS) device.
- Passive Serial (PS)
  - Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device, or a microprocessor to control the configuration process synchronously and supply the configuration data serially to an Arria GX FPGA.
- JTAG
  - Configures Arria GX FPGAs via the IEEE Standard 1149.1 interface.
Parallel—Used for faster configuration
- Fast Passive Parallel (FPP)
  - Uses an external intelligent host, such as a PC, an EPC device, or a microprocessor to control the configuration process synchronously and supply the configuration data in a parallel manner to the Arria GX FPGA.
- Passive Parallel Asynchronous (PPA)
  - Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process asynchronously and supply the configuration data in a parallel manner to the Arria GX FPGA.

For prototyping or debugging
- Using Altera^® Programming Cables
  - The Quartus^® II programmer supports configuring Arria GX FPGAs directly using PS or JTAG interfaces via Altera programming cables.
In the field
- Serial Configuration Devices Features (PDF)
  - The Arria GX FPGA gets its configuration data from the EPCS device automatically after power up. However, you must program the EPCS device first.
- Enhanced Configuration Devices Data Sheet (PDF)
  - The EPC device configures the Arria GX device automatically after power up. However, you must program the EPC device first.
- MAX Series Configuration Controller Using Flash Memory White Paper (PDF)
  - A MAX^® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs.
  - Source code (ZIP)