DSPI: Serial Peripheral Interface Master/Slave

from Digital Core Design

Features

• Serial peripheral interface (SPI) master
  • Master and multi-master operation
  • System error detection
    • Mode fault error
    • Write-collision error
  • Interrupt generation
  • Support for speeds up to 1/4 of system clock
  • Eight slave select lines
  • Bit rates generated: 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, and 1/512 of system clock
  • Support for four transfer formats
  • Simple interface for easy connection to microcontrollers
• SPI slave
  • Slave operation
  • System error detection
  • Interrupt generation
  • Support for speeds up 1/4 of system clock
  • Support for four transfer formats
  • Simple interface for easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states
• Technology-independent hardware description language (HDL) source code

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. DSPI — Serial Peripheral Interface Master/Slave

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Description

The DSPI core is a fully configurable SPI master/slave device that allows the user to configure the polarity and phase of the serial clock signal, sck.

The DSPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. The serial clock line synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data is simultaneously transmitted and received.

The DSPI core is a technology-independent design that can be implemented in a variety of process technologies.

The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates are as high as 1/4 of the clock rate. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of four different bit rates for the serial clock.

The DSPI core automatically drives the slave select outputs (SS7O-SS0O). This operation is controlled by the slave select control register (SSCR). The DSPI core also addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode fault detector automatically disables the DSPI output drivers if more than one SPI device simultaneously attempts to become the bus master.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

HDL source code package includes:

• VHDL or Verilog source code
• VHDL or Verilog test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim^® automatic simulation macros
  • Full tests with reference responses
• Synthesis scripts

Encrypted megafunction package includes:

• EDIF or Text Design File (.tdf) netlist optimized for particular technology
• Core instantiation inside Quartus^® II software environment
• Symbol, include, assigments, and configuration files
• Compilation, simulation, and programming ready project

Each package includes:

• Technical documentation
  • Installation notes
  • HDL core specification
  • Data sheet
• Example application
• Technical support
  • Intellectual property (IP) core implementation support
  • Three months of maintenance, including phone and e-mail support

Contact Information

For additional information, contact Digital Core Design at:

Wroclawska 94
41-902 Bytom
Poland
Tel: +48 32 2828266
Fax: +48 32 2827437
E-mail: aleads@dcd.pl
URL: http://www.digitalcoredesign.com