DFPMU - Floating Point Math Unit

from Digital Core Design

Features

• Direct replacement for C float software functions that include: +, -, *, /,==, !=,>,=, <=,
• C interface supplied for Nios^® embedded processors and 8051 compilers
• No programming required
• Single-precision real format support - float type
• 16-bit word and 32-bit short integer format supported - integer types
• Flexible arguments and result registers
• Capability to perform of the following functions:
  • Addition, subtraction
  • Multiplication, division
  • Square root
  • Change of sine, absolute value
  • Examine input data, comparison
  • Sine, cosine, tangent, and arctangent
  • 16-bit, 32-bit integer to float
• Exceptions to built-in routines
• Masking of each exception indicator:
  • Precision lack (PE)
  • Underflow result (UE)
  • Overflow result (OE)
  • Invalid operand (IE)
  • Division by zero (ZE)
  • Denormal operand (DE)
• Fully synthesizable, static synchronous design with no internal tri-states
• Optimized for use with Altera^® Nios embedded processor

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. Block Diagram

Description

DFPMU uses the specialized Coordinate Rotation Digital Computer (CORDIC) and standard algorithms to compute math functions. It has built-in conversion instructions that will convert integer types to floating-point types and vice versa. DFPMU supports single-precision real numbers, and 16- and 32-bit integers. The input numbers format is in accordance with the IEEE-754 standard and can be used with the 32-bit Nios embedded processor.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

HDL Source code packages includes:

• VHDL or Verilog source code
• VHDL or Verilog testbench environment
  • Active-HDL automatic simulation macros
  • ModelSim^® automatic simulation macros
  • Full tests with reference responses
• Synthesis scripts

Encrypted megafunction packages includes:

• EDIF or text design file (TDF) netlist optimized for particular technology
• Core instantiation inside Quartus^® II software
• Symbol, include, assignment, and configuration files
• Compilation, simulation, and programming ready projects

Each package includes:

• Technical documentation
  • Installation notes
  • HDL core specification
  • Data sheet
• Example application
• Technical support
  • Intellectual property (IP) core implementation support
  • Three months of maintenance including phone and e-mail support

Contact Information

For additional information, contact Digital Core Design at:

Digital Core Design
Wroclawska 94
41-902 Bytom
Poland
Tel. +48 32 282 82 66
Fax +48 32 282 74 37
E-mail: aleads@dcd.pl
Website: http://www.digitalcoredesign.com