Streaming Multi-port SDRAM Memory Controller

from Microtronix Inc.

Features

• Supports 10 local bus RD/WR interface ports
• FIFO port interface enables independent clock domains for memory and local buses
• Source-synchronous date capture design:
  • Supports a memory data rate up to 200 and 300 MHz in Cyclone^® and Stratix^® FPGAs
  • Reduces the memory design process to a two-step compilation process
• Supports all standard SDR, DDR, DDR2, and mobile DDR devices
• Memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles
• Each system port has user-configurable cache to boost performance over single cache intellectual property (IP) cores
• Configurable FIFO depth and release threshold parameter minimizes system wait-states
• Simple RD or WR local port interface for ease of integration with other chip logic
• Memory data widths: 8/16/32/64 bits
• Local bus width from 8 to 128 bits
• FIFO—memory data transfers are handled as burst memory accesses
• Round-robin port arbitration
• Configuration GUI streamlines design process
• Support for On-Die Termination
• IP functional VHDL simulations model
• Supported devices: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix II GX, Stratix III, and Arria^® GX FPGAs 
• You can customize the core to video/image applications, additional ports, or for other user requirements
• Source code license available (VHDL)
• OpenCore Plus evaluation

Block Diagram

Figure 1 shows the block diagram for Microtronix Streaming Multi-Port SDRAM Memory Controller.

Description

The Microtronix Streaming Multi-port SDRAM Memory Controller IP Core is designed for building low latency multi-master streaming data systems. Incorporating advanced design features, the core enables maximum system clock rates using low-speed FPGAs and standard memory devices. It supports SDR, DDR, DDR2, and mobile DDR device families in a single IP core, assuring designers of a smooth low-risk migration path with changing technology. The core integrates the following into one easy-to-use core:

• A burst SDRAM memory controller core
• A port arbitrator
• An intelligent look-ahead FIFO controller

One of the key performance features of the Microtronix Streaming Memory Controller IP core is a proprietary source-synchronous design technique used for capturing the high-speed DDR data from the memory devices independent of the round-trip delay. The method makes IP core timings independent of the PCB layout trace length signal delay and any associated impedance variance of the board fabrication process. The source-synchronous clocking also frees the IP core design task from the PCB design step and reduces the FPGA design compilation to a simple two-step process.

This proprietary source-synchronous data capture technology also removes the extra resynchronization clocks required by phase-locked loop (PLL)-based designs boosting the performance of the memory system by 20 percent. This clocking concept also expands data capture timing margins extending temperature performance and enabling faster timing closure in the design fitting process. An additional benefit is that the memory controller can support mobile DDR memory devices.

The local ports can be configured for either RD or WR access. By using FIFO buffers to bridge the time domain of the local bus ports to the SDRAM memory clock domain, each port can be independently clocked at their optimal design frequency. You can also configure port FIFO buffer depth (from 16 to 2,048 bytes) to the match characteristics of the streaming data device and provided for extended burst pipelined memory cycles, eliminating CAS latency overhead encountered using a short burst access controller. Internally the FIFO buffers are partitioned into two banks allowing the input and output of each to be filled or emptied simultaneously.

The core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system. Using the intuitive Microtronix GUI interface, with a few clicks of a mouse, you can create a multi-port system, a design task which would normally take several months of effort.

The core can easily be customized for bus data width or other bus arbitration schemes. Additional RD/WR system ports can be supported.

Device Utilization Examples

Table 1 lists the typical device utilization results for the Multi-Port Streaming SDRAM Memory Controller.

Note:

1. The logic element (LE) count for Stratix II FPGAs is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus^® II software.

Deliverables

Streaming Multi-port SDRAM Memory Controller IP Core Designer Package, (PN: 6248-01-01)

• Encrypted source code
• GUI Configuration interface
• ModelSim^®/VHDL precompiled simulations library
• Reference designs for Altera development kits
• Single or multi-user licensing
• Technical support

Contact Information

For additional information, contact Microtronix Datacom Ltd. at:

9-1510 Woodcock Street
London, ON, Canada N6H 5S1
Tel: +1 (519) 690-0091
Fax: +1 (519) 690-0092
Email: sales@microtronix.com
URL: www.microtronix.com