from Microtronix Inc.
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Features
- Supports 10 local bus RD or WR interface ports
- FIFO interface enables independent clock domains for memory and local bus ports
- Source-synchronous DDR2 data capture design:
- Supports a memory data rate up to 267 and 400 MHz in Cyclone® and Stratix® FPGAs
- Reduces the memory design process to a two-step compilation process
- Memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles
- Each system port has user configurable FIFO cache to boost performance over single cache intellectual property (IP) cores
- Configurable FIFO depth and release threshold parameter minimizes system wait-states
- Simple RD or WR local port interface for ease of integration with other chip logic
- Memory data widths up to 128 bits
- Local bus width from 16 to 256 bits
- FIFO—memory data transfers are handled as burst memory accesses
- Round-robin port arbitration (standard)
- Configuration GUI streamlines design process
- Support for On-Die Termination
- IP functional VHDL simulations model
- Supported devices: Stratix II, Stratix II GX, Stratix III, and Arria® GX FPGAs
- You can customize the core for video/image application, additional ports, or for other user requirements
- Source code license available (VHDL)
- OpenCore Plus evaluation
Block Diagram
Figure 1 shows the block diagram for Microtronix HyperDrive Multi-Port DDR2 Memory Controller.
Figure 1. Microtronix HyperDrive Multi-Port DDR2 Controller
Description
The Microtronix HyperDrive Multi-Port DDR2 Memory Controller IP Core raises FPGA-based hardware designs to a whole new level of performance. Built around a new DDR2 state machine controller, the controller operates at half the frequency of the memory interface, improving timing closure and performance. A proprietary Microtronix source-synchronous data capture technique enables 400-MHz DDR2 performance in a Stratix III FPGA.
The memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles. The core integrates: a burst DDR2 memory controller core, a port arbitrator, and an intelligent look-ahead FIFO controller into one easy-to-use core.
The core supports up to ten independently clocked RD or WR streaming-data devices operating from one shared high-bandwidth memory system. With a few clicks of a mouse and within minutes, using the intuitive Microtronix GUI interface, you can create a multi-port system, a design task which would normally take several months of effort.
The core can easily be customized for bus data width or other bus arbitration schemes. Additional RD/WR system ports can be supported.
Device Utilization Examples
Table 1 lists the typical device utilization results for the HyperDrive Multi-Port DDR2 Memory Controller.
| Table 1. Typical Device Utilization for the Megafunction | ||||||
| Altera Target Devices |
Speed Grade | Utilization | Performance fMAX |
Parameter Setting | ||
|---|---|---|---|---|---|---|
| LEs (1) | M4K Blocks | |||||
| Arria GX | -6 | 900 | 1 | 300 MHz | Contact Microtronix | |
| Stratix III | -2 | 900 | 1 | 400 MHz | Contact Microtronix | |
| Stratix II | -2 | 900 | 1 | 400 MHz | Contact Microtronix | |
| Stratix II GX | -2 | 900 | 1 | 400 MHz | Contact Microtronix | |
- The logic element (LE) count for Stratix II FPGAs is based on the number of adaptive look-up tables (ALUTs) used for the design, as reported by the Quartus® II software.
Deliverables
HyperDrive Multi-Port DDR2 Memory Controller IP Core Designer Package (PN: 6243-01-01)
- Encrypted source code
- GUI configuration interface
- ModelSim®/VHDL precompiled simulations library
- Reference designs for Altera and Microtronix development kits
- Single or multi-user licensing
- Technical support
Contact Information
For additional information, contact Microtronix Datacom Ltd. at:
Microtronix
9-1510 Woodcock Street
London, ON, Canada N6H 5S1
Tel: +1 (519) 690-0091
Fax: +1 (519) 690-0092
Email: sales@microtronix.com
URL: www.microtronix.com
