40-Gbps and 100-Gbps Ethernet MegaCore Function

from Altera

Altera offers the 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) MegaCore^® function intellectual property (IP) cores in beta for building systems with very high throughput-rate standard Ethernet connections. These IEEE 802.3ba^TM-2010 40-Gbps and 100-Gbps Ethernet standard compliant media access control (MAC) and PHY (PCS+PMA) IP cores enable an Altera^® device to interface to another device or to an optical transceiver module and, in turn, to 40GbE and 100GbE networks.

Figure 1 illustrates an example of Altera 40GbE or 100GbE MAC with a XLAUI or CAUI interface in an Altera device. 40GbE and 100GbE are two different IP cores.

Figure 1. 40GbE or 100GbE MegaCore Function in an Altera Device

Supported Devices

• Stratix^® IV GT FPGA

Features

• Compliant with the IEEE 802.3ba^TM-2010 40-Gbps and 100-Gbps Ethernet standard
• XLAUI and CAUI physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps
• 40GbE and 100GbE physical coding sublayer (PCS) soft IP cores implemented in FPGA fabric
• 40GbE and 100GbE MAC soft IP cores with configurable feature set
• Support full 40Gbps and 100Gbps wire speed traffic respectively
• Deficit idle count (DIC)
• Automatic Ethernet flow control
• Programmable maximum receive frame length up to 9,600 bytes
• 16 programmable MAC addresses and receiver (RX) packet filtering based on MAC addresses
• Promiscuous (transparent) and non-promiscuous (filtered) operation modes
• Programmable received frame filtering with cyclical redundancy check (CRC), oversized and undersized frame error
• 64-bit statistics counters for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
• Transmitter (TX) and RX FIFO in MAC provide pass-through or store and forward frame processing
• Avalon^® Streaming (Avalon-ST) interface for data path to client application with the start of packet (SOP) in 64-bit lane0's most significant byte (MSB) when FIFO and adapter option is used (100GbE: 512 bits at 312.5+ MHz; 40GbE: 256 bits at 312.5+ MHz)
  • Custom streaming interface with SOP possible on any 64-bit lane MSB when FIFO and adapter option is not used (100GbE: 320 bits at 312.5+ MHz; 40GbE: 128 bits at 312.5+ MHz)
• Avalon Memory-Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
• Management data input/output (MDIO) or 2-wire serial interfaces for managing different
  optical modules
• Additional synthesizable testbench to demonstrate and test Ethernet IP core operation
• Passed functional and performance tests with 40/100Gb Ethernet test equipment

Ease of Use

• Complete 40GbE and 100GbE examples to start your design quickly
  • RTL and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
  • Verification testbench and hardware example designs
  • Development boards
    • 100G Development Kit, Stratix IV GT Edition

Protocol Solution

For other 40GbE and 100GbE solutions, see Altera wireline solutions.

Performance 

Typical expected resource utilization and performance figures for this IP core are provided in
the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF).

Technical Support 

For technical support on this IP core, please visit Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.