Forward Discrete Cosine Transfer (DCT)

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Features

• Supports FLEX^® 10KE, ACEX^® 1K and APEX^™ 20KE devices
• High clock speed
• Low gate count
• 8 x 8 DCT block size
• Continuous one symbol per clock cycle
• 8 bpp inputs, 11 bit output coefficients, 10 bit cosine coefficients and 15 bit internal computations precision
• No internal RAM requirements
• Internal zero-level shifting on input samples
• Low latency (82 cycles)
• Fully synchronous, without internal tri-states, with asynchronous reset
• Available in VHDL
• Inverse DCT and combined DCT/IDCT also available

Block Diagram

Description

The discrete cosine transform (DCT) core implements the two dimensional (2D) forward DCT (2D-DCT) on an 8 x 8 block of samples. Hence, it is appropriate for DCT-based image or video encoders and can be used as a core for the JPEG, MPEG1, MPEG2, MPEG4, H.261, and H.263 standards. The core is based on the row-column computational architecture.

The DCT core is designed for reuse in ASIC and programmable logic devices. The design is fully synchronous with positive edge clocking and no internal tri-state buffers. It offers high performance, with a low gate count, and can be used in any multimedia, digital video, or digital printing application.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device	Speed Grade	Utilization			Performance (fMAX)	Availability
		LCs (1)	I/O Pins (2)	ESBs
FLEX 10KE(EPF10K100EQC208)	-1	2927	69	192 bits	58 MHz	Now
ACEX 1K(EP1K100QC208)	-1	2923	69	192 bits	52 MHz	Now
APEX 20KE(EP20K100ETC144)	-1	3219	69	192 bits	80 MHz	Now

Notes:

1. Optimized for speed.
2. Assuming all core I/O is routed off-chip.

Deliverables

• Encrypted Licenses
  • Post-synthesis AHDL
  • Assignment & Configuration File (.acf)
  • Symbol File (.sym)
  • Include File (.inc)
  • Vectors for testing the functionality of the megafunction
• HDL Source Licenses
  • VHDL source RTL
  • Synthesis scripts (LeonardoSpectrum)
  • Simulation scripts (ModelSim)
  • Documentation (user's guide)
  • Extensive HDL testbench that instantiates:
  • Example design
  • Input signal generator
  • A set of expected results
  • Design support
  • Reference C source code (bit-accurate model)

Contact Information

For additional information, contact CAST. Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
WWW: http://www.cast-inc.com

The DCT core is licensed from Alma Technologies S.A.