from Barco Silex
     |
Features
- Multichannel high-definition (HD) video standard
- Compliant with Digital Cinema Initiatives (DCI) recommendation
- Compliant with International Organisation for Standardisation (ISO) or International Electrotechnical Commision (IEC) 15444-1: JPEG2000 Image Coding System
- Integrated intellectual property (IP) core offering an Altera® FPGA solution for HD and DCI JPEG 2000 video applications
- Support for lossless and lossy compression schemes
- Configurable output bit rate: 250 Mbps, 500 Mbps, 1 Gbps, or lossless
- Full-frame encoding (no tiling)
- Dynamically configurable encoder parameters, including:
- 5/3 or 9/7 wavelet filter, 0 to 6 levels
- Configurable tile size up to 1080p, 2K, and 4K
- Up to 12-bit precision per color component
- XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for inverse color transform (ICT) or residual color transform (RCT)
- Configurable bit rate on a frame-by-frame basis with three selectable regulation modes
- Component-position-resolution-layer (CPRL) or layer-resolution-component-position (LRCP) progression order
- Specific quantization factor per subband
- Fully synchronous design
Block Diagram
Figure 1 shows a block diagram of the MegaCore® function.
Description
Capitalizing on its long-term experience with JPEG 2000 hardware processing, Barco Silex offers a large portfolio of JPEG 2000 solutions including this real-time hardware encoder engine that is optimized for DCI and HD video applications. The core architecture offers a flexible and high-speed solution to the performance challenges of cinema, broadcast and post-production applications. It is able to sustain the high encoding requirements of the large DCI frame formats, including 4096 x 2160 resolution and frame rates up to 48 frames per second (fps).
The BA110 IP core is a JPEG 2000 hardware encoder dedicated to DCI and HD video applications. It applies JPEG 2000 encoding on un-tiled large color frames. It generates streams compliant with the ISO or IEC 15444-1 specifications (JPEG 2000).
The IP core performs the following video compression operations of the normalized encoding process:
- Entropy encoding
- Quantization
- Discrete wavelet transform (DWT)
- ICT or RCT
- Rate allocation
The input interface of the BA110 supports video formats with 4:4:4 or 4:2:2 chroma sub-sampling and 12-bit precision color components. It generates a JPEG 2000 stream at its output interface. In case of 4:4:4 operation this stream is DCI compliant.
The core is optimized for speed and is able to deal with the demanding DCI and HD processing requirements. It is able to provide a single-chip FPGA solutions for all 2K at 24 fps, 2K at 48 fps, 4K at 24 fps, 720p30/60, 1080i and 1080p30/60 distributions.
The flexible FPGA architecture allows the user to build a secure encoder by integrating Barco Silex cryptography encoders— Advanced Encryption Standard (AES).
Device Utilization and Performance
Table 1 lists the typical device utilization results for the MegaCore function.
Table 1. Typical Device Utilization |
||||
|---|---|---|---|---|
Resolution |
Configuration | Frame Rate | Bandwidth | Minimum target devices |
| 720p60 | 1 channel 1280x720 YUV 4:2:2, 10 bits |
60 fps | 200 Mbps | Stratix® III E110 or L110 FPGA Cyclone® IV GX110 or E115 FPGA Arria® II GX 125 FPGA Stratix IV GX110 or E110 FPGA All Stratix V |
| 1080i60 | 1 channel 1920x540 YUV 4:2:2, 10 bits |
60 fps | 200 Mbps | Stratix II E110 or L110 FPGA Arria II GX 125 FPGA Stratix IV GX110 or E110 FPGA All Stratix V |
| 1080p30 | 1 channel 1920x1080 YUV 4:2:2, 10 bits |
30 fps | 400 Mbps | Stratix II E110 or L110 FPGA Arria II GX 125 FPGA Stratix IV GX110 or E110 FPGA All Stratix V |
| 1080p60 | 1 channel 1920x1080 YUV 4:2:2, 10 bits |
60 fps | 400 Mbps | Stratix II E110 or L110 FPGA Arria II GX 125 FPGA Stratix IV GX110 or E110 FPGA All Stratix V |
| 2K | 1 channel 2048x1080 RGB 4:4:4, 12 bits |
24 fps |
250 Mbps |
Stratix II E110 or L110 FPGA Arria II GX 125 FPGA Stratix IV GX110 or E110 FPGA All Stratix V |
| 2K 3D | 2 channels 2048x1080 RGB 4:4:4, 12 bits |
24 fps per channel |
250 Mbps per channel |
Stratix III L200 or E260 FPGA Arria II GX 190 FPGA Stratix IV GX180 or E230 FPGA All Stratix V |
4K |
1 channel 4096x2160 RGB 4:4:4, 12 bits |
24 fps |
500 Mbps |
Stratix III E260 or L340 Arria II GX 260 Stratix IV GX230 or E230 All Stratix V |
Deliverables
- Pre-synthesized netlist
- Functional testbench that demonstrates IP usage
- Implementation example with constraint file
- Data sheet and other documentation
Related Links
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park,
Rue du Bosquet 7,
B-1348 Louvain-la-Neuve,
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
Email: barco-silex@barco.com
URL: www.barco-silex.com
