DFPAU – Floating-Point Arithmetic Unit

from Digital Core Design

Features

• Direct replacement for C float software functions such as: +, -, *, /,==, !=,<=, <=, <,>
• C interface supplied for Altera^® Nios^® embedded processors, 8051 compilers
• No programming required
• Single-precision real format support: float type
• Flexible arguments and result registers location
• Performs the following functions:
  • FADD, FSUB—addition, subtraction
  • FMUL, FDIV—multiplication, division
  • FSQRT—square root
  • FCHS, FABS—change of sign, absolute value
  • FXAM—examine input data
  • FUCOM—comparison
• Exception built-in routines
• Masks each exception indicator
  • Precision lack: PE
  • Underflow result: UE
  • Overflow result: OE
  • Invalid operand: IE
  • Division by zero: ZE
  • Denormal operand: DE
• Fully synthesizable, static synchronous design with no internal tri-states
• Optimized for use with the Nios II embedded processors

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. DFPAU — Floating-Point Arithmetic Unit

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Description

DFPAU uses the specialized algorithms to compute arithmetic functions. It supports the addition, subtraction, multiplication, division, square root, comparison, absolute value, and change of sign of a number. DFPAU supports single-precision real numbers of IEEE-754 standard. DFPAU is well-suited for use with the 32-bit Nios II processor.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Deliverables

Hardware description language (HDL) source code package includes:

• VHDL or Verilog source code
• VHDL or Verilog test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim^® automatic simulation macros
  • Full tests with reference responses
• Synthesis scripts

Encrypted megafunction package includes:

• EDIF or Text Design File (.tdf) netlist optimized for particular technology
• Core instantiation inside Quartus^® II software environment
• Symbol, include, assigments, and configuration files
• Compilation, simulation, and programming ready project

Each package includes:

• Technical documentation
  • Installation notes
  • HDL core specification
  • Data sheet
• Example application
• Technical support
  • Intellectual property (IP) core implementation support
  • Three months of maintenance, including phone and e-mail support

Contact Information

For additional information, contact DIgital Core Design at:

Wroclawska 94
41-902 Bytom, Poland
Tel: +48 32 2828266
Fax: +48 32 2827437
E-mail: aleads@dcd.pl
URL:  www.dcd.com.pl