HardCopy Device Questions and Answers

Following are the most frequently asked questions about Altera^® HardCopy^® devices.

A. The HardCopy II ASIC is a non-reprogrammable device seamlessly migrated from a design that is prototyped in a Stratix^® II FPGA. Because of its unique FPGA front-end design process, the HardCopy series offer the lowest risk and fastest time-to-market of any other ASIC. The HardCopy II family builds on the success of Altera’s first two generations of HardCopy ASICs: the 0.18-µm HardCopy APEX™ devices and 0.13-µm HardCopy Stratix devices. Based on a fine-grained architecture of transistor cells, called HCells, HardCopy II ASICs are fabricated on the same advanced 90-nm process from the Taiwan Semiconductor Manufacturing Company (TSMC) as the Stratix II FPGA family. HardCopy II ASICs offer up to 2.2 million ASIC gates and 8.8 Mbits of RAM, 350-MHz performance and low cost, and consume less than 50 percent of the core power of the Stratix II FPGA design.

Q. What is the difference between HardCopy II ASICs and previous generations of HardCopy ASICs?

A. Previous generations of HardCopy ASICs were based on the same logic element (LE)-based architecture as the FPGA prototype. HardCopy II ASICs are based on fine-grained architecture to offer significantly lower cost per gate, higher densities, higher performance, and more features as compared to previous HardCopy generations. The fine-grained architecture of HardCopy II devices is made up of HCells, which were designed to support a seamless FPGA migration while providing the density, cost, performance, and power benefits of ASIC technology.

Q. What process technology are HardCopy II ASICs built on?

A. HardCopy II ASICs are based on a 1.2-V, 90-nm, all-layer-copper process technology from TSMC. HardCopy II ASICs are manufactured in the same facility as Stratix II FPGAs to ensure a seamless migration from FPGA prototypes to HardCopy II devices. Stratix II FPGAs utilize low-k dielectric and are manufactured on 300-mm wafers.

Q. How many members are there in the HardCopy II ASIC family, and in what packages are they available?

A. The HardCopy II ASIC family includes five members with logic densities up to 2.2 million usable gates, 8.8 Mbits of embedded RAM, 951 I/O pins, 384 18 x 18 multipliers, and 12 phase-locked loops (PLLs). HardCopy II ASICs are available in four high-performance flip-chip FineLine BGA packages (484 to 1,508 pins) and one cost-optimized wire bond package (484 pins).

Feature	HC210W (1)	HC210	HC220	HC230	HC240
*Table 1. HardCopy II Family Overview*
ASIC Gates (2)	1M	1M	1.6M	2.2M	2.2M
Additional Gates for Digital Signal Processing (DSP) Blocks (3)	0	0	0.3M	0.7M	1.4M
Total RAM Bits	875,520	875,520	3,059,712	6,345,216	8,847,360
Phase-Locked Loops (PLLs)	4	4	4	8	12
Maximum I/O Pins (4)	300	334	494	698	951
Packages	484-pin Wire Bond FBGA (5)	484-pin FBGA	672-pin FBGA 780-pin FBGA	1,020-pin FBGA	1,020-pin FBGA 1,508-pin FBGA
FPGA Prototype Options	EP2S30 EP2S60 EP2S90	EP2S30 EP2S60 EP2S90	EP2S60 EP2S90 EP2S130	EP2S90 EP2S130 EP2S180	EP2S180

Notes:

HC210W devices are in a wire bond package. Devices in wire bond packages offer different speed and power characteristics than devices in flip-chip packages.
Available for both logic and DSP functions as implemented in the Stratix II FPGA prototype.
Additional ASIC gates available for Stratix II DSP block functions.
Preliminary information. I/O pin count comprised of user and clock I/O pins.
FBGA: FineLine BGA package

Q. When will HardCopy II ASICs be available?

A. All HardCopy II ASIC devices and packages are available today. Design in Quartus II software, prototype with Stratix II FPGAs, and Altera's HardCopy Design Center will migrate the design to a low cost, pin-compatible HardCopy II device.

Q. Are HardCopy II ASICs pin-compatible with Stratix II FPGAs?

A. Yes. Pin-compatibility with the FPGA is a significant benefit of HardCopy II ASICs.

Q. What are the advantages of HardCopy II ASICs over competing offerings?

A. The HardCopy II ASIC family offers a low-risk approach through the use of pin-compatible in-system verification using FPGAs. The result is lower development cost, improved time-to-market, and improved flexibility. In addition, by allowing Altera’s HardCopy Design Center to perform the migration work, the customer’s design team can focus on innovation rather than on reducing the costs of an existing design.

Q. How are HardCopy II ASICs customized for each design?

A. The HardCopy II base arrays are developed with logic and hard IP embedded into them. Additionally, the array is customized with the top two metal layers for each customer design. This allows for fast turnaround time as well as low development cost and unit cost.

Q. What are the benefits of the fine-grained architecture in HardCopy II ASICs?

A. Small die area and lower cost. The fine-grained architecture delivers high-density logic in a small die size. As a result, HardCopy II ASICs can offer a 1 million ASIC gate device with 350-MHz performance for very low cost.

HardCopy Features

Q. What is the density range for HardCopy II ASICs? Which Stratix II FPGAs can be used for prototyping?

A. HardCopy II ASICs are available in densities ranging between 1 million and 2.2 million ASIC gates, with 0.8 Mbits to 8.8 Mbits of embedded RAM. Design engineers can prototype and test their designs in the EP2S30, EP2S60, EP2S90, EP2S130, and EP2S180 members of the Stratix II FPGA family.

Q. How does the performance of HardCopy II ASICs compare to that of Stratix II FPGAs?

A. Core logic benefits significantly from the HCell-based architecture, the removal of programmability, shorter routing lines, and overall reduced die size. The result is an average f_MAX improvement for core logic up to 100 percent.

As with previous generations of HardCopy ASICs, HardCopy II devices are fabricated on the same process technology as the prototype FPGA. Hence, any hard IP, such as I/O or memory, offers the same high performance as the Stratix II FPGA prototype.

Q. How much power reduction can customers expect by moving to a HardCopy II ASIC from a Stratix II FPGA?

A. Customers will see over a 50 percent reduction in both dynamic and static power when moving from a Stratix II FPGA to a HardCopy II ASIC. The power reduction is a result of significant die size reductions that occur when transitioning a design from a FPGA prototype to a HardCopy II device. Further power reduction occurs by connecting power only to the transistors used in the design. To reduce risk in design migration and ensure pin compatibility, HardCopy II I/O pin power is designed to be equivalent to that of the Stratix II FPGA. As a result, the I/O power remains the same as the FPGA prototype.

Q. How many PLLs are embedded in HardCopy II ASICs and which types are supported?

A. Up to 12 on-chip PLLs are available on the largest HardCopy II ASIC. HardCopy II ASICs support two types of PLLs: enhanced PLLs for general-purpose PLL clocking and fast PLLs optimized for high-speed differential I/O interfaces. Both provide advanced frequency synthesis capabilities.

Q. What high-speed differential I/O electrical standards do HardCopy II ASICs support?

A. HardCopy II ASICs support the same high-speed differential I/O standards that can be prototyped in Stratix II FPGAs, such as LVDS and LVPECL.

Q. What high-speed I/O interface protocols are supported in Stratix II FPGAs?

A. Stratix II FPGAs support many of the latest high-bandwidth bus protocols, including the SPI-4.2, SFI-4, XSBI, HyperTransport™, RapidIO^®, NPSI, and UTOPIA IV protocols for applications such as interface bridging, backplanes, and chip-to-chip communications.

Q. Which external memory interfaces do HardCopy II ASICs support?

A. The HardCopy II ASIC family contains dedicated interface circuitry to meet the performance requirements of the latest SRAM and DRAM devices, including SDRAM, DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDRII SRAM, and ZBT SRAM. External memory devices can be easily connected to HardCopy II ASICs to provide additional storage capacity outside of the abundant on-chip memory resources without causing performance bottlenecks. You can purchase Altera- or third-party-developed IP memory controller cores, download royalty-free reference designs from the Altera website, or develop their own customized cores for your specific applications.

Q. What happens to the unused I/O pins in a HardCopy II ASIC in boundary scan?

A. Just as in an FPGA, the unused I/O pins are still present in the base of the HardCopy II ASIC and connect into the Joint Test Action Group (JTAG) chain.

Q. Are HardCopy II ASICs available in the industrial or military temperature ranges?

A. Yes, all HardCopy II ASICs are available in the industrial temperature range with junction temperatures ranging from -40°C to 100°C.

HardCopy II ASICs in a full military temperature range, from -55°C to 125°C are planned for late 2007. You can begin design work today and prototype with the Stratix II FPGAs today.

Q. Are HardCopy II ASICs available in RoHS-compliant packages?

A. Yes, HardCopy II ASICs are available in RoHS-compliant packages.

Design Migration

Q. Which prototype Stratix II device do I choose for my HardCopy II design?

A. Depending on the constraining resource, different Stratix II devices can be used to prototype a HardCopy II design. Since Stratix II FPGAs support vertical migration, a number of pin-compatible prototype options exist. The HardCopy II Device Resource Guide in Quartus II design software advises you as to the most efficient prototype FPGA to choose.

Q. Which HardCopy II ASIC can I migrate to from my Stratix II design?

A. A HardCopy II Device Resource Guide is generated every time you compile a Stratix II design using Quartus II software version 4.2 or later. This report will guide you as to which HardCopy II ASIC is suitable for your design.

Q. What is the difference between the I/O in the Stratix II FPGA and the HardCopy II ASIC?

A. The HardCopy II ASIC has been designed to have equivalent I/O performance and electrical characteristics as the Stratix II FPGA in which the design is prototyped.

Q. How is testability addressed in HardCopy ASICs?

A. Base arrays for all HardCopy ASICs are embedded with testability circuits. HardCopy II ASICs come standard with built-in self test (BIST) circuits for memory, PLLs, and boundary scan logic for the design. Altera’s HardCopy II ASICs do not require any functional vectors from customers. Using automatic test pattern generation (ATPG) vectors, HardCopy II ASICs are tested on the structural design, resulting in very high test coverage of approximately 99 percent.

Q. What design files do customers hand over to the HardCopy Design Center for the migration process?

A. Customers must submit their Quartus II Archive File (.qar), which contains everything needed for developing a HardCopy ASIC. The file is generated using the HardCopy Files Wizard in the Quartus II development software. The Altera HardCopy Design Center manages the migration process.

Q. How long does it take to migrate a design to a HardCopy ASIC?

A. Once all the required design guidelines are met and Altera accepts the design, the design can be migrated to a HardCopy series ASIC in two to four weeks. After the customer has approved the timing results, HardCopy prototypes are available within five weeks. Production units are delivered within eight weeks from when you reviewed and approved the prototypes.

Design Software

Q. What features are included in the Quartus II design software to support HardCopy II ASICs?

A. The Quartus II software includes the Hard Copy II Advisor, which provides development guidelines for successful HardCopy II design submission to Altera's HardCopy Design Center. It reports the tasks completed and tasks you still need to complete.

In addition, Quartus II software offers the HardCopy II Device Resource Guide and floorplan designing capability, along with TimeQuest SDC-based timing analysis and power estimation.

Q. Which synthesis vendors support the new HardCopy II ASICs?

A. HardCopy II ASICs are supported by Cadence, Mentor Graphics, Synplicity, and Altera’s Quartus II integrated synthesis tools by targeting a Stratix II device. Due to the parallel FPGA and HardCopy ASIC design flow, no further synthesis tools are required.

Q. Do I need to use additional design software to migrate from a Stratix II FPGA to a HardCopy II ASIC?

A. No. You can use the same Quartus II design software to migrate your Stratix II FPGA design (including any IP that is part of the design) to a HardCopy II ASIC. Additional licensing fees may apply for AMPP^SM (Altera Megafunction Partners Program) IP.

Intellectual Property

Q. What intellectual property is available for HardCopy II ASICs?

A. You can use any intellectual property (IP) core available for Stratix II FPGAs with the same seamless migration path to HardCopy II ASICs. More information is available at the Altera IP MegaStore™ web site.

Q. Is the Nios II embedded processor supported in HardCopy II ASICs?

A. Yes, the 32-bit RISC Nios^® II embedded processor offers continued support for Nios II features such as the simultaneous multi-master Avalon^® switch fabric, custom instructions, and advanced debugging.

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