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オンライン資料： アプリケーション・ノート

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日本語版資料は、英語版を翻訳したもので、内容に相違が生じる場合には原文を優先します。
こちらの日本語版は参考用としてご利用ください。設計の際には、最新の英語版で内容をご確認ください。

 

タイトル バージョン リリース日 容量 資料パートナンバ
アプリケーション・ノート
AN 567: Quartus II 分離デザイン・フロー

ver 1.0, Jun 2009, 3 MB

1.0Jul 200911 MBAN-567-1.0/JP
AN 539：アルテラFPGA デバイスの CRC によるエラー検出およびリカバリのテスト方法

ver 1.1, Jan 2009, 406 KB


     AN539 Design Example (425 KB) 		1.1Jul 2009620 KBAN-539-1.1/JP
AN 521: Cyclone IIIアクティブ・パラレル・リモート・システム・アップグレードのリファレンス・デザイン

ver 1.1, Aug 2009, 994 KB


     AN521 Design Files (1 MB) 		1.0Jul 20092 MBAN-521-1.0/JP
AN 520: DDR3 SDRAM インタフェースの終端およびレイアウト・ガイドライン

ver 1.1, May 2009, 909 KB

1.1Nov 20092 MBAN-520-1.1/JP
AN 519: Stratix IV デザイン・ガイドライン

ver 1.1, May 2009, 493 KB

1.1Jan 2010945 KBAN-519-1.1/JP
AN 517: SOPC Builder による高性能 DDR、DDR2、DDR3、SDRAM の使用

ver 1.0, Apr 2008, 1 MB


     AN 517 Design Files (2 MB) 		1.0Jul 20092 MBAN-517-1.0/JP
AN 514: Stratix IV FPGA における消費電力の最適化

ver 1.0, May 2008, 221 KB

1.0Jul 2009402 KBAN-514-1.0/JP
AN 509: MAX II CPLD を使用した SDIO デバイスのマルチプレックス

ver 1.0, Dec 2007, 198 KB


     AN 509 Design Example (721 KB) 		1.0Feb 2008297 KBAN-509-1.0/JP
AN 508: Cyclone III 同時スイッチング・ノイズ（SSN）デザイン・ガイドライン

ver 1.0, Dec 2007, 379 KB

1.0Nov 2009773 KBAN-508-1.0/JP
AN 507:Cyclone III デバイスにおけるPLL リコンフィギュレーションの実装

ver 1.0, Jan 2008, 739 KB


     Design Example 1: an507_de1_display.zip (204 KB)
     Design Example 2: an507_de2_dynphase.zip (84 KB) 		1.0Jan 2010891 KBAN-507-1.0/JP
AN 502: MAX II CPLD への SMBus コントローラの実装

ver 1.0, Dec 2007, 129 KB


     AN 502 Design Example (2 MB) 		1.0Feb 2008316 KBAN-502-1.0/JP
AN 501: MAX II CPLD を使用したパルス幅変調

ver 1.0, Dec 2007, 104 KB


     AN 501 Design Example (279 KB) 		1.0Jan 2008242 KBAN-501-1.0/JP
AN 500: MAX II CPLD を使用した NAND フラッシュ・メモリ・インタフェース

ver 1.0, Dec 2007, 137 KB


     AN 500 Design Example (187 KB) 		1.0Dec 2007698 KBAN-500-1.0/JP
AN 499: MAX II CPLD を使用したモバイル SDRAM インタフェース

ver 1.0, Dec 2007, 109 KB


     AN 499 Design Example (450 KB) 		1.0Feb 2008259 KBAN-499-1.0/JP
AN 498: MAX II CPLD のオート・ストップおよびオート・スタート機能を使用した LED の点滅

ver 1.0, Dec 2007, 104 KB


     AN 498 Design Example (168 KB) 		1.0Feb 2008258 KBAN-498-1.0/JP
AN 497: MAX II CPLD を使用した LCD コントローラ

ver 1.0, Dec 2007, 133 KB


     AN 497 Design Example (2 MB) 		1.0Feb 2008333 KBAN-497-1.0/JP
AN 496: MAX II CPLD の内蔵オシレータの使い方

ver 1.0, Dec 2007, 362 KB


     AN 496 Design Example (230 KB) 		1.0Feb 2008643 KBAN-496-1.0/JP
AN 495: MAX II CPLD を使用した IDE/ATA コントローラ

ver 1.0, Dec 2007, 155 KB


     AN 495 Design Example (418 KB) 		1.0Feb 2008286 KBAN-495-1.0/JP
AN 494: MAX II CPLD の I2C バス・インタフェースを使用した GPIO ピンの拡張

ver 1.0, Dec 2007, 193 KB


     AN 494 Design Example (273 KB) 		1.0Feb 2008299 KBAN-494-1.0/JP
AN 493: MAX II CPLD を使用した I2C バッテリ・ゲージ・インタフェース

ver 1.0, Dec 2007, 171 KB


     AN 493 Design Example (465 KB) 		1.0Feb 2008276 KBAN-493-1.0/JP
AN 492: MAX II CPLD を使用した CF+ インタフェース

ver 1.0, Dec 2007, 145 KB


     AN 492 Design Example (346 KB) 		1.0Feb 2008272 KBAN-492-1.0/JP
AN 491: MAX II CPLD を使用したオート・スタート

ver 1.0, Dec 2007, 119 KB


     AN 491 Design Example (245 KB) 		1.0Feb 2008271 KBAN-491-1.0/JP
AN 489: MAX II デバイスの UFM の使用

ver 1.0, Dec 2007, 161 KB


     AN 489 Design Example (551 KB) 		1.0Feb 2008335 KBAN-489-1.0/JP
AN 488: MAX II CPLD を使用したステッパ・モータ・コントローラ

ver 1.0, Dec 2007, 100 KB


     AN 488 Design Example (350 KB) 		1.0Feb 2008261 KBAN-488-1.0/JP
AN 487: MAX II CPLD による SPI-I2S 変換

ver 1.0, Dec 2007, 138 KB


     AN 487 Desgin Example (589 KB) 		1.0Feb 2008306 KBAN-487-1.0/JP
AN 486: MAX II CPLD による SPI-I2C 変換

ver 1.0, Dec 2007, 144 KB


     AN 486 Design Example (385 KB) 		1.0Feb 2008321 KBAN-486-1.0/JP
AN 485: MAX II CPLD を使用したシリアル・ペリフェラル・インタフェース・マスタ

ver 1.0, Dec 2007, 117 KB


     AN 485 Design Example (305 KB) 		1.0Feb 2008248 KBAN-485-1.0/JP
AN 484: SMBus による MAX II CPLD での GPIO ピンの拡張

ver 1.0, Dec 2007, 120 KB


     AN 484 Design Example (2 MB) 		1.0Feb 2008280 KBAN-484-1.0/JP
AN 483: トリプル・スピード・イーサネット・データ・パスのリファレンス・デザイン

ver 1.1, Jun 2009, 2 MB

1.0Jul 20082 MBAN-483-1.0/JP
AN 478: Quartus II ソフトウェアでのFPGA ベースのパラレル・フラッシュ・ローダの使用

ver 1.0, Nov 2007, 861 KB

1.0Apr 20092 MBAN-478-1.0/JP
AN 477: FPGA およびHardCopy デバイスとのRGMII インタフェースの設計

ver 2.0, Jan 2010, 519 KB

1.0Feb 2009399 KBAN-477-1.0/JP
AN 469: Stratix III デザイン　ガイドライン

ver 1.1, May 2008, 628 KB

1.0Apr 2008912 KBAN-469-1.0/JP
AN 466: Cyclone III デザイン・ガイドライン

ver 1.2, Nov 2008, 1 MB

1.0Dec 20071 MBAN-466-1.0/JP
AN 462: ALTMEMPHY メガファンクションを使用した複数のメモリ・インタフェースの実装

ver 1.3, Apr 2009, 784 KB


     Example Design for AN 462: top.qar (715 KB) 		1.0Nov 2007836 KBAN-462-1.0/JP
AN 458: Nios IIブート方法の応用1.0Jun 2008575 KBAN-458-1.0/JP
AN 456: PCI Express 高性能リファレンス・デザイン

ver 1.2, Aug 2009, 379 KB

1.0Sep 20071 MBAN-456-1.0/JP
AN 455: CIC 補償フィルタの解説

ver 1.0, Apr 2007, 268 KB

1.0Nov 2009492 KBAN-455-1.0/JP
AN 454: Stratix III デバイスにおけるPLL リコンフィギュレーションの実装

ver 2.0, Dec 2009, 868 KB


     Design Examples 1 (412 KB)
     Design Examples 2 (236 KB) 		1.2Nov 2009864 KBAN-454-1.2/JP
AN 453: HardCopy II のフィッティング技術

ver 2.0, Nov 2008, 716 KB

1.0Oct 20072 MBAN-453-1.0/JP
AN 449: Stratix II および Stratix II GX デバイスの外部メモリ・インタフェース実装のためのデザイン・ガイドライン

ver 1.2, Sep 2007, 284 KB

1.0Jul 2007573 KBAN-449-1.0/JP
AN 448: Stratix IIIの消費電力管理デザイン・ガイド

ver 1.3, May 2007, 201 KB

1.3Jul 2007422 KBAN-448-1.3/JP
AN 447 : Cyclone III デバイスと3.3V/3.0V/2.5V LVTTL/LVCMOS I/Oシステムのインタフェース

ver 2.0, Nov 2009, 396 KB

1.0Mar 2007622 KBAN-447-1.0/JP
AN 446: SignalTap II エンベデッド・ロジック・アナライザを使用したNios II システムのデバッグ

ver 1.2, Jun 2008, 257 KB


     signal_tap_test software file (4 KB) 		1.2Jul 2009531 KBAN-446-1.2/JP
AN 445: Cyclone III デバイスの DDR & DDR2 SDRAM インタフェース実装のためのデザイン・ガイドライン

ver 2.2, Jun 2009, 2 MB


     AN 445 Design Example (572 KB) 		2.0Jul 20084 MBAN-445-1.0/JP
AN 444: デュアル DIMM DDR2 SDRAM メモリ・インタフェースのデザイン・ガイドライン

ver 1.1, May 2009, 7 MB

1.0Jan 20082 MBAN-444-1.0/JP
AN 437: Stratix III FPGA の消費電力の最適化

ver 2.0, Aug 2007, 219 KB

1.0Nov 2006677 KBAN-437-1.0/JP
AN 436: Stratix III デバイスの DDR3 SDRAM インタフェース実装のためのデザイン・ガイドライン

ver 4.0, Nov 2008, 2 MB


     AN 436 Design Files (11 MB) 		1.0Sep 20072 MBAN-436-1.0/JP
AN 435: Stratix III デバイスの DDR および DDR 2 SDRAM インタフェース実装のためのデザイン・ガイドライン

ver 2.0, Aug 2008, 2 MB


     AN 435 Design Files (3 MB) 		1.0Jun 20072 MBAN-435-1.0/JP
AN 428: MAX II CPLD のデザイン・ガイドライン

ver 1.1, Dec 2007, 425 KB

1.1Mar 2008811 KBAN-428/JP
AN 426: MAX II CPLD を使用したアナログ・キーボード・エンコーダ

ver 1.0, Jul 2006, 308 KB

1.0Jul 2006436 KBAN-426-1.0/JP
AN 422: MAX II CPLD を使用したポータブル・システムにおける消費電力の管理

ver 1.0, Jul 2006, 265 KB

1.0Jul 2006496 KBAN-422-1.0/JP
AN 417: C2H コンパイラによるファンクションの高速化： チェックサム付Scatter-Gather DMA

ver 1.1, Jul 2006, 424 KB


     Scatter-Gather DMA Design Files (6 KB) 		1.1Sep 2009286 KBAN-417-1.1/JP
AN 411: Stratix II デバイスの PLL タイミング1.0Nov 20072 MBAN-411-1.0/JP
AN 410: I/O 制御およびレジスタ・データ保持による MAX II ISP のアップデート

ver 1.0, Mar 2006, 126 KB


     ISP SRAM Download Design Files (11 KB) 		1.0Mar 2006280 KBAN-410-1.0/JP
AN 409: altlvds メガファンクションおよび外部 PLL オプションを使用した Stratix II デバイスのデザイン例

ver 1.0, Mar 2006, 244 KB


     Design Example (7 MB) 		1.0Oct 2007743 KBAN-409-1.0/JP
AN 408: DDR2 メモリ・インタフェース終端、ドライブ強度、および負荷に関するデザイン・ガイドライン

ver 2.1, Jul 2008, 4 MB


     SII Simulation Example (3 KB)
     SIII Simulation Example (3 KB) 		1.2Jul 20071 MBAN-408-1.2/JP
AN 404: FFT/IFFTブロック浮動小数点スケーリング

ver 1.0, Oct 2005, 110 KB

1.0Sep 2008660 KBAN-404-1.0/JP
AN 398: SOPC Builder による DDR/DDR 2 SDRAM の使用

ver 1.1, Aug 2006, 775 KB

1.0Jul 2006854 KBAN-398-1.0/JP
AN 392: 複数のレガシーDDR/DDR2 SDRAM コントローラ・インタフェースの実装2.0Jan 2008866 KBAN-392-2.0/JP
AN 373: Avalon ビデオ入力モジュール

ver 1.0, Dec 2004, 154 KB

1.0Nov 2009551 KBAN-373/JP
AN 367: Stratix II デバイスによる PLL リコンフィギュレーションの実装1.0Dec 2004570 KBAN-367-1.0/JP
AN 360: POS-PHY Level 4 MegaCore ファンクション用シミュレーション・モデルのアップデート

ver 1.1, Dec 2004, 63 KB

1.1Dec 2004490 KBAN-360-1.1/JP
AN 357: アルテラFPGAデバイスの CRC によるエラー検出およびリカバリ

ver 1.4, Jul 2008, 371 KB

1.4Jul 2009558 KBAN-357-1.4/JP
AN 356: Cyclone および Stratix 対応、シリアル・デジタル・インタフェース・リファレンス・デザイン

ver 1.1, Aug 2004, 155 KB

1.1Aug 2004274 KBAN-356-1.1/JP
AN 351: Nios IIエンベデッド・プロセッサ・デザインのシミュレーション

ver 1.2, Nov 2008, 323 KB


     AN 351 Software Files (6 KB) 		1.1Jun 20082 MBAN-351-1.1/JP
AN 342: DDR SDRAM とStratix デバイスおよび Stratix GX デバイスとのインタフェース

ver 2.0, Dec 2005, 428 KB

1.0Apr 2004428 KBAN-342-1.0/JP
AN 340: アルテラのソフトウェア・ライセンス

ver 2.3, Mar 2009, 824 KB

2.0Jul 20082 MBAN-340-2.0/JP
AN 339: Stratix GX対応、シリアル・デジタル・インタフェース・リファレンス・デザイン

ver 3.3, May 2007, 288 KB

3.0Dec 2005420 KBAN-339-3.0/JP
AN 333: SOPC Builderにおけるペリフェラルの開発1.0Apr 2004487 KBAN-333-1.0/JP
AN 328: Stratix II デバイスによる DDR2 SDRAM インタフェース

ver 6.0, Oct 2009, 3 MB


     ALTMEMPHY Example (604 KB)
     Legacy PHY Example (330 KB) 		3.1May 20061 MBAN-328-3.1/JP
AN 327: DDR SDRAM と Stratix II デバイスのインタフェース

ver 3.2, Sep 2008, 938 KB

3.0Feb 20061 MBAN-327-3.0/JP
AN 326: Stratix II、Stratix II GX、Stratix、Stratix GXデバイスで実現するQDRII+およびQDRIIのインタフェース

ver 5.1, May 2008, 2 MB

5.0Jul 20084 MBAN-326-5.1/JP
AN 320: OpenCore Plus 評価機能によるメガファンクションの評価

ver 1.6, Nov 2007, 307 KB

1.4Aug 2007468 KBAN-320/JP
AN 315: 高速FPGAのプリント基板の設計ガイドライン

ver 1.1, Feb 2004, 2 MB

1.1Feb 20046 MBAN-315-1.1/JP
AN 311: ASIC から FPGA への移行に関するデザイン手法およびガイドライン

ver 3.1, Apr 2009, 286 KB

1.0Jul 2003897 KBAN-311-1.0/JP
AN 282: StratixおよびStratix GXデバイスでのPLLリコンフィギュレーションの実装1.0Jan 20031,000 KBAN-282-1.0/JP
AN 224: 高速ボード・レイアウト・ガイドライン

ver 1.2, Aug 2009, 494 KB

1.0Nov 2002707 KBAN-224-1.0/JP
AN 132: アルテラのPLDによる マルチ・プロトコル・ラベル・スイッチングの実現方法

ver 1.0, Jan 2001, 177 KB

1.0Jan 2001168 KBA-AN-132-01/JP
AN 131: Mercury デバイスの汎用PLL使用方法

ver 1.1, Oct 2001, 616 KB

1.1Oct 2001568 KBA-AN-131-1.1/JP
AN 129: アルテラのデバイスとIPファンクションによるW-CDMAシステムの実現

ver 1.0, Sep 2000, 196 KB

1.0Sep 2000183 KBA-AN-129-01/JP
AN 122: エンベデッド・プロセッサによる ISP と ICR に Jam STAPL を使用する方法

ver 2.0, Jun 2003, 218 KB


     IDCODE.ZIP version 3.0 5/17/04 file (13KB) (14 KB) 		1.0Mar 2003260 KBAN-122-1.0/JP
AN 117: アルテラ・デバイスがサポートする標準 I/O 規格の使用方法

ver 2.2, Dec 2001, 1 MB

1.0Oct 1999157 KBA-AN-117-1.0/JP
AN 115: APEXデバイスの ClockLock と ClockBoost 機能の使用方法

ver 2.6, Nov 2003, 557 KB

2.2Oct 2001588 KBAN-115-2.2/JP
AN 114: 高集積BGA パッケージを使用したアルテラ・デバイスの設計

ver 5.1, Dec 2007, 574 KB

5.0Jul 2006641 KBAN-114-5.0/JP
AN 112: APEX 20K デバイスのプロダクト・ターム・ロジック実現方法

ver 1.0, Apr 1999, 184 KB

1.0Apr 1999182 KBA-AN-112-01/JP
AN 110: APEX 20K デバイスのゲート算出方法

ver 1.01, Sep 1999, 169 KB

1.0Apr 199990 KBA-AN-110-01.0/JP
AN 106: 2.5 V デバイスの設計法

ver 1.01, Jul 1999, 352 KB

1.0Jan 1999215 KBA-AN-106-01.0/JP
AN 102: Leonardo Spectrum ソフトウェアによる FLEX 10K デバイスの性能改善方法

ver 1.0, Jun 1999, 450 KB

1.0Mar 1999245 KBA-AN-102-01.01/JP
AN 94: MAX7000 デバイスのタイミング

ver 2.0, May 1999, 216 KB

1.0Jan 199867 KBA-AN-094-01/JP
AN 92: FLEX 6000 デバイスのタイミング

ver 2.0, May 1999, 244 KB

1.0Jan 199894 KBA-AN-107-01/JP
AN 91: FLEX 10K デバイスのタイミング

ver 2.0, May 1999, 301 KB

1.0Jan 1998130 KBA-AN-091-01/JP
AN 81: 表面実装用デバイスの半田リフローに関するガイドライン

ver 4.0, Jun 2002, 147 KB

2.0Jun 2002337 KBAN-081-04/JP
AN 75: 高速動作ボードの設計

ver 4.0, Nov 2001, 768 KB

2.0Jan 199889 KBA-AN-75-2.0/JP
AN 74: アルテラ・デバイスの消費電力評価方法

ver 3.1, Jul 2001, 512 KB

2.0Jan 199871 KBA-AN-074-2.0/JP
AN 42: アルテラ・デバイスのメタスタビリティ

ver 4.0, May 1996, 167 KB

3.0Jan 199876 KBA-AN-042-03/J
AN 597: Getting Started Flow for Board Designs New 1.0Mar 2010149 KBAN-597-1.0
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode Updated
     AN580_scripts.zip (17 KB) 		2.0Feb 2010423 KBAN-580-2.0
AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices Updated 2.1Jan 20103 MBAN-558-2.1
AN 554: How to Read HardCopy PrimeTime Timing Reports Updated 2.0Mar 2010554 KBAN-554-2.0
AN 550: Using the DLL Phase Offset Feature in Stratix FPGAs and HardCopy ASICs Updated
     altmemphy_ext_dll.zip (48 KB)
     altmemphy_int_dll.zip (47 KB)
     static_dll.zip (18 KB) 		2.0Mar 2010547 KBAN-550-2.0
AN 540: Nios II MPU Usage New
     Design Files for AN 540 (221 KB) 		1.0Mar 2010385 KBAN540-1.0
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices Updated
     Design Example for AN 461 (3 MB) 		1.2Feb 2010986 KBAN-461-1.2
AN 431: PCI Express to External Memory Reference Design Updated 1.3Feb 2010408 KBAN-431-1.3
AN 592: Cyclone IV Design Guidelines 1.0Nov 2009483 KBAN-592-1.0
AN587: DPRIO and Multiple Instances SDI Application 1.0Aug 20091,002 KBAN-587-1.0
AN 581: High Definition Video Reference Design (V2) 1.0Nov 20091 MBAN-581-1.0
AN 569: SDI Flywheel Video Decoder Reference Design 1.0May 20091 MBAN-569-1.0
AN 548: Nios II Compact Configuration System for Cyclone III
     Design Files for AN 548 (597 KB) 		1.0Nov 2008320 KBAN-548-1.0
AN 533:Automotive Information and Entertainment Reference Designs 1.3Nov 20093 MBAN-533-1.3
AN 532: An SOPC Builder PCI Express Design with GUI Interface
     Design Files for AN 532 (5 MB) 		1.0Jun 2008285 KBAN-532-1.0
AN 531: Reducing Power with Hardware Accelerators
     Design Files for AN 531 (1 MB) 		1.0May 2008151 KBAN-531-1.0
AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs 1.0May 2008208 KBAN-530-1.0
AN 529: Via Optimization Techniques for High-Speed Channel Designs 1.0May 2008690 KBAN-529-1.0
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing 1.0May 20081 MBAN-528-1.0
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families
     Design Examples for AN 522 (37 KB) 		2.0Nov 2009856 KBAN-522-2.0
AN 512: Using the Design Security Feature in Stratix III Devices 1.1Mar 20091 MBAN-512-1.1
AN 507: Implementing PLL Reconfiguration in Cyclone III Devices
     Design Example 1: an507_de1_display.zip (204 KB)
     Design Example 2: an507_de2_dynphase.zip (84 KB) 		1.0Jan 2008739 KBAN-507-1.0
AN 490: MAX II CPLDs as Voltage Level Shifters
     AN 490 Design Example (147 KB) 		1.0Dec 2007323 KBAN-490-1.0
AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer 1.0Jul 20082 MBAN-481-1.0
AN 433: Constraining and Analyzing Source-Synchronous Interfaces 2.1Nov 20091 MBAN-433-2.1
AN 432: Using Different PLL Settings Between Stratix II and HardCopy II Devices Updated 1.2Mar 2010149 KBAN-432-1.2
AN 386: Using the Parallel Flash Loader with the Quartus II Software
     Flash Memory (873 bytes)
     Nios Design (567 KB) 		5.0Dec 20092 MBAN-386-5.0
AN 386: Using the Parallel Flash Loader with the Quartus II Software
     Flash Memory (873 bytes)
     Nios Design (567 KB) 		5.0Dec 20092 MBAN-386-5.0
AN 370: Using the Serial FlashLoader With the Quartus II Software 3.1Apr 20091 MBAN-370-3.1
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices
     ALTMEMPHY Example (604 KB)
     Legacy PHY Example (330 KB) 		6.0Oct 20093 MBAN-328-6.0
AN 601: Serial Digital Interface Reference Design for Arria II GX Devices
     Design Files for AN 601 (3 MB) 		1.0Dec 2009582 KBAN-601-1.0
AN 600: Serial Digital Interface Reference Design for Stratix IV Devices
     Design Files for AN 600 (1 MB) 		1.0Dec 2009586 KBAN-600-1.0
AN599: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design1.0Dec 20091,019 KBAN-599-1.0
AN 595: Vectored Interrupt Controller Usage and Applications
     Example Designs for AN595 (503 KB) 		1.0Nov 2009246 KBAN595-1.0
AN 593: Anti-Tamper Protection for Cyclone III LS Devices1.0Oct 2009626 KBAN-593-1.0
AN 589: Using the Design Security Feature in Cyclone III LS Devices1.0Sep 20091 MBAN-589-1.0
AN 588: 10-Gbps Ethernet Hardware Demonstration Reference Design1.1Dec 20091 MBAN-588-1.1
AN 586: Porting the Jam STAPL and Jam STAPL Byte-Code Players to an Embedded System1.0Aug 2009176 KBAN-586-1.0
AN585: Simulation Debugging Using Triple Speed Ethernet Testbench
     AN585: Test Cases (3 MB) 		1.0Aug 2009368 KBAN-585-1.0
AN 584: Timing Closure Methodology for Advanced FPGA Designs
     AN 584: Design Examples (380 KB) 		1.0Aug 20091 MBAN-584-1.0
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs
     AN 583: VCC to VCCDPLL Spice Examples (159 KB) 		1.0Jul 2009889 KBAN-583-1.0
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices1.0May 20091 MBAN-578-1.0
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs2.0Dec 2009753 KBAN-577-2.0
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology1.0May 2009899 KBAN-574-1.0
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers
(Not applicable when designing with Stratix IV GX and Stratix IV GT engineering sample devices) 		1.1Dec 2009768 KBAN-573-1.1
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices
(Not applicable when designing with Stratix IV GT engineering sample devices) 		2.0Jan 2010284 KBAN-572-2.0
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices1.0Jun 2009549 KBAN-571-1.0
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices
(Not applicable when designing with Stratix IV GT engineering sample devices) 		1.0Jun 20091 MBAN-570-1.0
RapidIO Interoperability with TI 6488 DSP Reference Design
(AN568: RapidIO Interoperability with TI 6488 DSP Reference Design) 		1.0May 2009883 KBAN568-1.0
AN 563: Arria II GX Design Guidelines1.0Feb 2009752 KBAN-563-1.0
AN561: Stratix II GX 10GbE Loopback Reference Design1.1Oct 2009549 KBAN-561-1.1
AN 559: High Definition Video Reference Design (V1)1.0Dec 20081 MBAN-559-1.0
AN557: Stratix III to Stratix IV E Cross-Family Migration Guidelines2.0Sep 2009924 KBAN-557-2.0
AN556: Using the Design Security Feature in Arria II GX and Stratix IV Devices1.1Jun 20091 MBAN-556-1.1
AN 553: Debugging Transceivers
     AN 553: Design Files (2 MB) 		1.0Jan 20091 MBAN-553-1.0
AN 551: SDI-ASI Auto Detect Reference Design for Stratix II GX Devices1.0Nov 2008232 KBAN-551-1.0
AN 549: Managing Designs with Multiple FPGAs1.0Sep 2008776 KBAN-549-1.0
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
     MAX II Hibernation Design (87 KB) 		1.0Jan 2009256 KBAN-547-1.0
AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs
     Example_design.zip (578 KB) 		2.0Dec 20092 MBAN-545-2.0
AN 544: Digital IF Modem Design with the DSP Builder Advanced Blockset1.0Aug 2008976 KBAN-544-1.0
AN543: Debugging Nios II Software Using the Lauterbach Debugger
     Example Design for AN543 (6 MB) 		1.0Apr 2009278 KBAN543-1.0
AN 542: High Definition Video Monitoring Reference Design (M5)1.2Nov 2008814 KBAN-542-1.2
AN 541: SerialLite II Hardware Debugging Guide1.0Aug 20081 MBAN-541-1.0
AN 537: Implementing UNH-IOL Test Suite Compliance in Arria GX and Stratix II GX Gigabit Ethernet Designs
     carrier_detect_logic.zip (2 KB) 		1.0Sep 2008514 KBAN-537-1.0
AN 536: Design Guidelines for Preparing HardCopy II ASICs1.0Sep 20081 MBAN-536-1.0
AN527: Implementing an LCD Controller1.0May 2008344 KBAN-527-1.0
AN 526: 3GPP UMTS Turbo Reference Design2.0Jan 2010374 KBAN-526-2.0
AN 524: High Definition Video Monitoring Reference Design (M4)1.0Apr 2008567 KBAN-524-1.0
AN523: Cyclone III Configuration Interface Guidelines with EPCS Devices1.1Jun 2009966 KBAN-523-1.1
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices1.0May 20081 MBAN-518-1.0
AN 515: 24K FFT for 3GPP LTE RACH Detection1.0Nov 2008230 KBAN-515-1.0
AN 513: RapidIO Interoperability With TI 6482 DSP Reference Design2.0Nov 2008867 KBAN-513-2.0
AN 511: Polyphase Modulation Using a FPGA for High-Speed Applications1.0Feb 2008279 KBAN-511-1.0
AN 506: QR Matrix Decomposition2.0Mar 2008371 KBAN-506-2.0
AN 505: 3GPP LTE Turbo Reference Design2.0Jan 2010388 KBAN-505-2.0
AN 504: DSP System Design in Stratix III Devices
     Design Example 1: Parallel FIR (79 KB)
     Design Example 2: Multi-Channel FIR (20 KB)
     Design Example 3: MAC_FIR (vhdl) (21 KB)
     Design Example 4: Large Mult_Add (11 KB) 		1.0Feb 20081 MBAN-504-1.0
AN 503: Implementing OFDM Modulation for Wireless Communications1.0Jan 2008268 KBAN-503-1.0
AN 482: High Definition Video Monitoring Reference Design (M2)4.0Aug 2008621 KBAN-482-4.0
AN 480: 1536-Point FFT for 3GPP Long Term Evolution1.0Oct 2007154 KBAN-480-1.0
AN 479: Design Guidelines for Implementing LVDS Interfaces in Cyclone Series Devices1.1Jun 2009435 KBAN-479-1.1
AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices1.0Oct 2007391 KBAN-476-1.0
AN 475: Crest Factor Reduction for OFDMA Systems1.0Dec 2007362 KBAN-475-1.0
AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II Software1.2Mar 2008365 KBAN-474-1.2
AN 472: Stratix II GX SSN Design Guidelines1.0Aug 2007666 KBAN-472-1.0
AN 471: High-Performance FPGA PLL Analysis with TimeQuest1.0Aug 2007227 KBAN-471-1.0
AN 465: Implementing OCT Calibration in Stratix III Devices
     Design Example 1 (200 KB)
     Design Example 2 (74 KB)
     Design Example 3 (211 KB)
     Stratix III OCT Power Up Example (46 KB) 		1.0Nov 2007623 KBAN-465-1.0
AN 464: DFT/IDFT Reference design1.0Jun 2007187 KBAN-464
AN 463: Using ALTMEMPHY Megafunction with HardCopy II Structured ASICs1.0Jul 2007915 KBAN-463-1.0
AN 459: Guidelines for Developing a Nios II HAL Device Driver
     AN 459 Design Example (30 KB) 		2.0Nov 20082 MBAN-459-2.0
AN458: Alternative Nios II Boot Methods
     AN458 design example files (37 KB) 		1.1Sep 2008334 KBAN-458-1.1
AN 457: Integrating Uplink Desubchannelization and Ranging Modules for WiMAX1.0Feb 2007166 KBAN-457-1.0
AN 452: An OFDM Kernel for WiMAX
     WiMAX OFDMA Reference Design Web Page (8 KB) 		1.0Feb 2007319 KBAN-452-1.0
AN 451: Downlink Subchannelization for WiMAX1.0Feb 2007319 KBAN-451-1.0
AN 450: Uplink Desubchannelization for WiMAX1.0Feb 2007319 KBAN-450-1.0
AN 443: External PHY Support in PCI Express MegaCore Functions1.0May 2007435 KBAN-443-1.0
AN 442: Tool Flow for Design of Digital IF for Wireless Systems1.0May 20071 MBAN-442
AN 440: Accelerating Nios II Networking Applications
     Accelerating Nios II Networking Applications Design (3 MB) 		1.1Jun 2009179 KBAN-440-1.1
AN 439: Constellation Mapper and Demapper for WiMAX1.1May 2007250 KBAN-439-1.1
AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, Arria II GX, and Cyclone III Devices
     SIII_phase_shift (5 KB) 		4.1May 2009976 KBAN-438-4.1
AN 434: Channel Estimation & Equalization for Mobile WiMAX Basestations
     Channel Estimation & Equalization Reference Design (8 KB) 		1.1May 2007748 KBAN-434-1.1
AN 430: WiMAX OFDMA Ranging1.0Aug 2006769 KBAN-430-1.0
AN 429: Remote Configuration Over Ethernet with the Nios II Processor
     Application Note 429 Design Files (3 MB) 		2.0Mar 2009207 KBAN-429-2.0
AN 427: Video and Image Processing Example Design
     Video Processing Reference Design web page (12 KB) 		8.0Nov 20093 MBAN-427-8.0
AN 425: Using Command-Line Jam STAPL Solution for Device Programming3.0Jul 2009302 KBAN-425-3.0
AN424: I/O Simulations Using HSPICE1.0Jul 20063 MBAN-424-1.0
AN 423: Configuring the MicroBlaster Passive Serial Software Driver
     Source Code (149 KB) 		1.1Jun 2008211 KBAN-423-1.1
AN 421: Accelerating WiMAX DUC & DDC System Designs
     WiMAX DUC & DDC Reference Design Web Page (9 KB) 		2.2May 2007758 KBAN-421-2.2
AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
     Source Code (254 KB) 		1.1Jun 2008288 KBAN-418-1.1
AN 415: DDR and DDR2 SDRAM ECC Reference Design
     ECC Reference Design Files (242 bytes) 		1.0Jun 2006291 KBAN-415
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
     Source Code (221 KB) 		1.0May 2006145 KBAN-414-1.0
AN 413: Using Legacy Integrated Static Data Path and Controller Megafunction with HardCopy II Structured ASICs2.1Jul 2007227 KBAN-413-2.1
AN 412: A Scalable OFDMA Engine for WiMAX
     WiMAX OFDMA Reference Design Web Page		2.1May 2007359 KBAN-412-2.1
AN 411: Understanding PLL Timing for Stratix II Devices
     Design Example 1 (279 KB)
     Design Example 2 (233 KB) 		1.0Mar 20061 MBAN-411-1.0
AN 407: Automotive Audio Reference Design1.0Apr 20062 MBAN-407-1.0
AN 400: SMBus Interface for the User Flash Memory in MAX II Devices
     SMBus (Read/Write/Erase) Design Files (8 KB)
     SMBus (Read Only) Design Files (8 KB) 		1.0Sep 20051 MBAN-400-1.0
AN 396: Crest Factor Reduction1.0Jun 20071 MBAN-396
AN 395: Stratix II Professional FFT Co-Processor Reference Design1.0Aug 2005446 KBAN-395-1.0
AN 393: Stratix II Professional Filtering Lab1.0Aug 20051 MBAN-393-1.0
AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces
     three controller example (26 KB)
     two controller example (15 KB) 		2.0Jul 2007306 KBAN-392-2.0
AN 391: Profiling Nios II Systems
     AN 391 Profiler Example Files (15 KB) 		1.3Jul 2008406 KBAN-391-1.3
AN 388: High-Performance EMIF Bridge Core1.2Sep 2005435 KBAN-388
AN 387: Upgrading a FIR Compiler v3.1.x Design to v3.2.x1.0May 2005537 KBAN-387-1.0
AN 385: Using Stratix GX Transceivers for PCI Express1.0Jun 20054 MBAN-385-1.0
AN 384: Using Calibrated Series On-Chip Termination in Stratix II Devices
     User-Mode Calibration Reference Design (Quartus II Version 4.2 SP1) (233 KB)
     User-Mode Calibration Reference Design (Quartus II Version 5.0) (233 KB) 		1.0Apr 2005116 KBAN-384-1.0
AN 383: Cyclone II DDR2 SDRAM Demonstration1.0Apr 2005175 KBAN-383-1.0
AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver1.2Jun 2006630 KBAN-380-1.2
AN 379: Active Serial Memory Interface Controller Reference Design
     Design Files (11 KB) 		1.0Mar 2005191 KBAN-379-1.0
AN 377: Edge Detection Using SOPC Builder & DSP Builder Tool Flow1.0May 20051 MBAN-377-1.0
AN 376: Cyclone II Filtering Lab1.0May 20051 MBAN-376-1.0
AN 375: Cyclone II FFT Co-Processor Reference Design1.0May 2005566 KBAN-375-1.0
AN 372: Avalon LCD Controller1.0Dec 2004159 KBAN-372
AN 371: Automotive Graphics System Reference Design1.0Dec 2004195 KBAN-371
AN 369: AES3/EBU Reference Design
     AES3/EBU Reference Design Web Page (10 KB) 		1.1Feb 20051 MBAN-369
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
     Example 1: altpll_reconfig Design with the MIF (244 KB)
     Example 2: altpll_reconfig Design with Write Parameters (249 KB)
     Example 3: altpll_reconfig Design for Phase Shift Stepping (251 KB) 		2.1May 2009717 KBAN-367-2.1
AN 366: Understanding I/O Output Timing for Altera Devices1.0Jul 2006311 KBAN-366-1.0
AN 364: Edge Detection Reference Design1.0Oct 20041 MBAN-364-1.0
AN 363: FFT Co-Processor Reference Design1.0Oct 20041 MBAN-363-1.0
AN 362: Stratix II Filtering Lab1.0Oct 20041 MBAN-362-1.0
AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices1.3Jun 2006380 KBAN-361-1.3
AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator
     Parameter Selection Calculator (2 MB) 		2.0Sep 2008238 KBAN-359-2.0
AN 358: Thermal Management for FPGAs2.0Dec 2009260 KBAN-358-2.0
AN 355: Stratix II Device System Power Considerations1.0Jun 2004274 KBAN-355-1.0
AN 353: Reflow Soldering Guidelines for Lead-Free Packages2.0Feb 2009155 KBAN-353-2.0
AN 352: FPGA Peripheral Expansion & FPGA Co-Processing1.0Jul 2004552 KBAN352-1.0
AN 350: Upgrading Nios Processor Systems to the Nios II Processor1.1Jul 2006617 KBAN-350-1.1
AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices1.0May 2004280 KBAN-349-1.0
AN 348: Interfacing DDR SDRAM with Cyclone Devices1.1Jul 2004441 KBAN-348-1.1
AN 347: Farrow-Based Decimating Sample Rate Converter1.0Mar 2004256 KBAN-347-1.0
AN 346: Using the Nios II Configuration Controller Reference Designs1.2Mar 2009793 KBAN-346-1.2
AN 345: Altera Design Flow for Lattice Semiconductor Users1.1Jan 2005581 KBAN-345-1.1
AN 344: ASI Demonstration2.0Oct 2006145 KBAN-344-2.0
AN 343: OpenCore Evaluation of AMPP Megafunctions1.0Feb 2004294 KBAN-343-1.0
AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices2.3Aug 20091 MBAN-341-2.3
AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices1.0Nov 20031 MBAN-336-1.0
AN 335: POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features1.0Jan 2004282 KBAN-335-1.0
AN 334: ADI Parallel Port SDRAM Controller Reference Design1.3Jun 2005753 KBAN-334-1.3
AN 333: Developing Peripherals for SOPC Builder
     Slave Peripheral Design Files (455 KB)
     Streaming Slave 1C20 Design Files (1 MB)
     Streaming Slave 1S10 Design Files (1 MB)
     Streaming Slave 1S10ES Design Files (1 MB)
     Streaming Slave 1S40 Design Files (1 MB) 		1.0Apr 2004267 KBAN-333-1.0
AN 332: Link-Port Reference Design1.3Feb 20051 MBAN-332
AN 330: Connecting Altera 3.3-V PCI devices to a 5-V PCI Bus1.0Feb 2004112 KBAN-330-1.0
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices1.0Mar 2004165 KBAN-329-1.0
AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices3.1Nov 20052 MBAN-325-3.1
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems1.1Nov 2007386 KBAN-323-1.1
AN 322: Porting the Nios GERMS Monitor to Work with Different Flash Memories1.0Sep 2003139 KBAN-322-1.0
AN 317: Turbo Encoder Co-processor Reference Design1.2Oct 2003183 KBAN-317-1.2
AN 316: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs1.0Jul 2003402 KBAN-316-1.0
AN 314: Digital Predistortion Reference Design1.0Jul 20031 MBAN-314
AN 313: Implementing Clock Switchover in Stratix & Stratix GX Devices
     Clock Switchover Example Design (233 KB) 		1.0Jan 2004273 KBAN-313-1.0
AN 308: Building Embedded Processor Systems Using SOPC Builder & Excalibur Devices
     AN 308: Design Files (6 MB) 		1.0Mar 20031 MBAN-308-1.0
AN 307: Altera Design Flow for Xilinx Users
     an307_DesignExample.zip (4 KB) 		6.3Nov 20092 MBAN-307-6.3
AN 306: Implementing Multipliers in FPGA Devices3.0Jul 2004733 KBAN-306-3.0
AN 299: System Development Tools for Excalibur Devices1.1Jun 2003618 KBAN-299-1.1
AN 298: Reconfiguring Excalibur Devices Under Processor Control
     AN 298: Design Files (1 MB) 		1.0Feb 2003705 KBAN-298-1.0
AN 295: Gold Code Generator Reference Design1.0Mar 2003188 KBAN-295
AN 294: Crosspoint Switch Matrices in MAX II & MAX 3000A Devices
     16 x 16 Crosspoint Switch (6 KB)
     Customized Crosspoint Switch (7 KB) 		2.0Mar 2004205 KBAN-294-2.0
AN 293: Using MAX 7000B Devices to Replace I/O Drivers1.1Nov 2005233 KBAN-293-1.1
AN 287: Using Excalibur DMA Controllers for Video Imaging
     AN 287: Design Files (7 MB) 		1.1Feb 2003664 KBAN-287-1.1
AN 286: Implementing LED Drivers in MAX and MAX II Devices2.3Oct 2008164 KBAN-286-2.3
AN 284: Implementing Interrupt Service Routines in Nios Systems
     Example Code (5 KB) 		1.0Jan 2003335 KBAN-284-1.0
AN 283: Simulating Altera Devices with IBIS Models1.1Nov 2003166 KBAN-283-1.1
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices
     Example 1: Shift Register in LEs (340 KB)
     Example 2: altpll_reconfig Design with the MIF (192 KB)
     Example 3: altpll_reconfig Design (192 KB) 		2.0Dec 2005511 KBAN-282-2.0
AN 281: QPSK Modem Reference Design
     AN281 Design Files (98 MB) 		2.1Oct 20031 MBAN-281-2.1
AN 278: Excalibur Dynamic Reconfiguration with Linux Demonstration
     AN 278: Design Files (17 MB) 		2.0Jun 2003811 KBAN-278-2.0
AN 267: Rebuilding the Excalibur Dynamic Reconfiguration with Linux Demonstration1.0Jun 2003318 KBAN-267-1.0
AN 265: Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander2.0Mar 2004306 KBAN-265-2.0
AN 263: CORDIC Reference Design1.4Jun 2005323 KBAN-263
AN 247: Stratix GX to Mercury Interoperability1.2Jan 200482 KBAN-247-1.2
AN 245: Filtering Reference Design Lab3.0Dec 2004670 KBAN-245-3.0
AN 244: Using Run-From-Flash Mode with the Excalibur Bootloader1.0Sep 2002140 KBAN-244-1.0
AN 242: Excalibur Solutions - Simple Excalibur System
     AN 242: Design Files (468 KB) 		1.0Aug 2002245 KBAN-242-1.0
AN 240: Simulating Excalibur Systems1.0Sep 2002335 KBAN-240-1.0
AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices1.1Jan 2003177 KBAN-236-1.1
AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices1.0May 2003633 KBAN-228-1.0
AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices1.0May 2003456 KBAN-227-1.0
AN 223: PCI-to-DDR SDRAM Reference Design1.0May 2003507 KBAN-223-1.0
AN 213: Excalibur Remote Reconfiguration Demonstration Design
     AN 213: Design Files (2 MB) 		1.0Feb 20032 MBAN-213-1.0
AN 210: Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs2.0Nov 2002143 KBAN-210-2.0
AN 196: Excalibur Software Debugging Solutions1.2Aug 2002147 KBAN-196-1.2
AN 192: Excalibur Solutions - Embedded Stripe Performance Designs
     AN 192: Design Files (346 KB) 		1.2Nov 2002253 KBAN-192-1.2
AN 191: Excalibur Solutions - Using the Interrupt Controller
     AN 191: Design Files (370 KB) 		1.3Dec 2002202 KBAN-191-1.3
AN 189: Simulating Nios Embedded Processor Designs2.1Feb 20031 MBAN-189-2.1
AN 188: Custom Instructions for the Nios Embedded Processor1.2Sep 2002313 KBAN-188-1.2
AN 187: Booting Excalibur Devices
     AN 187: Design Files (574 KB) 		1.2Mar 2003632 KBAN-187-1.2
AN 186: Using Flexible-LVDS Circuitry in Mercury Devices1.1Nov 2002264 KBAN-186-1.1
AN 185: Thermal Management Using Heat Sinks2.1Mar 2002254 KBA-AN-185-2.1
AN 184: Simultaneous Multi-Mastering with the Avalon Bus1.1Apr 2002135 KBAN-184-1.1
AN 183: ZBT SRAM Controller Reference Design for APEX II Devices1.0Dec 2001211 KBA-AN-183-1.0
AN 181: Excalibur Solutions - Multi-Master Reference Design
     AN 181: Design Files (804 KB) 		2.3Nov 2002642 KBAN-181-2.3
AN 180: POS-PHY Level 4-POS-PHY Level 3 Bridge Reference Design1.02Oct 2001545 KBA-AN-180-1.02
AN 179: Designing with ESBs in APEX II Devices1.0Mar 20024 MBA-AN-179-1.0
AN 178: Estimating Nios Resource Usage & Performance1.0Sep 2001224 KBA-AN-178-1.0
AN 177: Excalibur Solutions-Using the Excalibur Stripe PLLs1.3Jul 2002300 KBA-AN-177-1.3
AN 173: Excalibur Solutions - DPRAM Reference Design
     AN 173: Design Files (326 KB) 		2.3Aug 2002208 KBA-AN-173-2.3
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices1.1Aug 2002141 KBA-AN-167-1.1
AN 166: Using High-Speed I/O Standards in APEX II Devices1.May 2003463 KBAN-166-1.8
AN 159: Using HSDI in Source-Synchronous Mode in Mercury Devices1.1Dec 2002246 KBAN-159-1.1
AN 156: Using General-Purpose PLLs with APEX II Devices 1.5Feb 2003431 KBAN-156-1.5
AN 143: Excalibur Solutions - Using the Expansion bus Interface1.0Oct 2002991 KBA-AN143-1.0
AN 142: Excalibur Solutions - Using the Embedded Stripe Bridges 2.1Jun 2002432 KBA-AN142-2.1
AN 141: Excalibur Solutions - Using the SDRAM Controller1.0Sep 2002926 KBA-AN141-1.0
AN 138: LVDS Signaling Using APEX Devices I/O Pins1.0May 2001229 KBA-AN-138-01
AN 134: Using Programmable I/O Standards in Mercury Devices2.1Dec 2002506 KBAN-134-2.1
AN 130: CDR in Mercury Devices1.0Feb 2001225 KBA-AN-130-01
AN 128: Implementing Voice Over Internet Protocol1.1Sep 2000188 KBA-AN-128-01.1
AN 120: Using LVDS in APEX 20KE Devices1.5Aug 20091 MBAN-120-1.5
AN 119: Implementing High-Speed Search Applications with Altera CAM
     Source code for fully associative cache (5 KB)
     Source code for direct mapped cache (5 KB) 		2.1Jul 20012 MBA-AN-119-2.1
AN 113: Plastic Package Reliability & Testing1.0Jun 1999180 KBA-AN-133-01
AN 111: Embedded Programming Using the 8051 and Jam Byte-Code1.2Sep 2008289 KBAN-111-1.2
AN 109: Using the HP 3070 Tester for In-System Programming1.2Jan 2003123 KBAN-109-1.2
AN 107: Using Altera Devices in Multi-Voltage Systems2.0Aug 2001207 KBA-AN-107-2.0
AN 101: Improving Performance in FLEX 10K Devices with the Synplify Software1.0Oct 1998696 KBA-AN-101-01
AN 100: In-System Programmability Guidelines 3.0May 1999217 KBAN-100-3.0
AN 95: In-System Programmability in MAX Devices1.5Sep 2005123 KBAN-095-1.5
AN 90: SameFrame Pin-Out Design for FineLine BGA Packages1.01Sep 2000277 KBA-AN-090-01.01
AN 83: Binary Numbering Systems1.0Apr 1997174 KBA-AN-083-01
AN 82: Highly Optimized 2-D Convolver1.0Feb 1997285 KBA-AN-082-01
AN 80: Selecting Sockets for Altera Devices3.0Jan 1999152 KBA-AN-080-03
AN 79: Understanding FLASHlogic Timing1.0Jun 1996311 KBA-AN-079-01
AN 78: Understanding MAX 5000 & Classic Timing3.0May 1999230 KBA-AN-078-03
AN 77: Understanding MAX 9000 Timing3.0May 1999239 KBA-AN-077-03
AN 76: Understanding FLEX 8000 Timing3.0May 1999207 KBA-AN-076-03
AN 73: Implementing FIR Filters in FLEX Devices1.0Feb 1998205 KBA-AN-073-01.01
AN 71: Guidelines for Handling J-Lead & QFP Devices4.0Jan 1999303 KBA-AN-071-04
AN 51: Using Programmable Logic for Gate Array Designs 1.0Jan 1996303 KBA-AN-051-01
AN 49: Implementing CRCCs in Altera Devices2.1Oct 2005146 KBAN-049-2.1
AN 46: ATM Packet Scheduler in FLEX 8000 Devices 1.0Mar 1995248 KBA-AN-046-01
AN 45: Configuring FLASHlogic Devices1.0Apr 1995159 KBA-AN-045-01
AN 43: Designing for MAX 9000 Devices1.0Aug 1995179 KBA-AN-043-01
AN 38: Configuring Multiple FLEX 8000 Devices2.01May 1994442 KBA-AN-038-2.01
AN 36: Designing with FLEX 8000 Devices2.0May 1994218 KBA-AN-036-02
AN 33: Configuring FLEX 8000 Devices3.03Jun 2000401 KBA-AN-033-3.03

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