- 100 percent instruction set compatible to all ColdFire family processors
- Supported by all existing ColdFire software ecosystems, including operating systems and tools
- 1-pin background debug mode (BDM), real-time debug (RTD) support, works with existing ColdFire debugging tools
- Optimized for the Altera® Cyclone® III FPGAs
- SOPC Builder compatible
- $0 licensing fee and $0 royalty for the core
- Commercial support available
- Fully synthesizable core
- Variable length RISC 16-bit, 32-bit, and 48-bit instructions
- 16 user-accessible, 32-bit wide general-purpose registers
- 32-bit data bus with 24-bit address bus supporting 16-MB linear addressing
- Independent, decoupled pipelines
- 2-stage instruction fetch pipeline (IFP)
- 2-stage operand execution pipeline (OEP)
- FIFO instruction buffer provides decoupling
The small-footprint V1 ColdFire core is designed for entry-level, 32-bit applications. It is designed to enhance system utilization resulting in the low power consumption, while giving more than ten times the performance of an 8-bit MCU.
The FPGA implementation of the V1 ColdFire core on Cyclone III FPGAs extends the ColdFire advantage to a new dimension. You can now create custom MCUs on demand, providing a unique way to add product differentiation. Because the V1 ColdFire core is 100 percent instruction set compatible with other ColdFire processors, newly created MCUs can reuse application code of its predecessors, saving development time.
Free of charge, the V1 ColdFire core is licensed exclusively by IPextreme. Delivered as an encrypted, SOPC Builder tool-compatible intellectual property (IP) core, you can combine the processor core with other embedded peripherals to create custom, exact-fit MCUs using the Quartus® II software (includes the SOPC Builder tool). The ecosystem-compatible debug core ensures that you can use all the familiar standard ColdFire development tools to create applications, including Freescale’s CodeWarrior and IAR’s Workbench for ColdFire development tools.