Altera understands the unique challenges facing military electronic systems designers. Cyclone® III FPGAs offer an unprecedented combination of low power, functionality, and low cost to meet stringent size, weight, and power (SWaP) requirements, enabling next-generation military applications. To accelerate proof-of-concept development, a rich set of software, intellectual property (IP), reference designs, and development kits are available.
The Cyclone III LS FPGA offers enhanced security features and design separation for single-chip encryption, all with the lowest power profile in the FPGA industry. Cyclone III LS FPGAs are the only FPGAs to offer high functionality (up to 200K logic elements, 8.2 Mbits of memory, and 396 multipliers) while consuming less than 1/4 W of static power.
Challenges
Military designs often operate in thermally challenging and space-constrained environments with stringent SWaP requirements. Product lifecycles can be anywhere from a few years to decades. Often prototype and design cycles span several years and systems must be flexible to support emerging and changing standards such as new software-defined radio waveforms. Single event upset (SEU) detection and information security are paramount concerns when designing high reliability systems.
Solution
Cyclone III FPGAs offer an unprecedented combination of low power, functionality, and security features to meet stringent SWaP requirements to enable next-generation military applications (refer to Table 1).
| Table 1. Key Military System Application Advantages of Cyclone III FPGAs | |
| Feature | Advantage |
|---|---|
| Low Power | The EP3CLS200 device includes 198K logic elements, a little more than 8-Mbits of memory, and 396 multipliers but only consume less than 1/4 W static power at Tj = 85°C. The EP3C120 device includes 119K logic elements, nearly 4-Mbits of memory, and 288 multipliers, also consuming less than 1/4 W static power at a junction temperature of 85°C. |
| Security | Cyclone III LS FPGAs include enhanced security features such as FIPS-197 (256-bit AES) encryption of the FPGA bitstream, uninterruptable internal oscillator, JTAG port protection, SEU detection circuitry, and the capability to "clear" the FPGA and volatile key storage. |
| Design Separation | A new feature in Quartus® II software that, in conjunction with IP, provides a solution for creating single-chip encryption on a single FPGA. |
| Abundant Memory at Every Density | Up to 8 Mbits of embedded memory and an increased memory-to-logic ratio for all Cyclone III device family members. |
| Digital Signal Processing (DSP) Multipliers | Up to 396 embedded 18-bit x 18-bit multipliers at up to 200-MHz performance to process DSP-intensive algorithms. |
| Nios® II Embedded Soft Processor | The world’s most versatile embedded soft processor, ideal for implementing a low-cost microcontroller. Also available in a DO-254 certifiable variant. |
| Small Form Factor Support | 0.8-mm spacing uBGA packages, bare die support, and custom multichip module support. All devices are offered in leaded and RoHS-compliant packages. |
| Industrial Temperature Support | Support for harsh operating environments from -40°C to 100°C. |
| SEU Detection | Dedicated cyclic redundancy check (CRC) circuitry ensures data integrity and is one of the best techniques for mitigating SEU problems or detecting glitches/faults. |
| End of Life Protection | Altera keeps its devices in production longer, reducing obsolescence risk management volume. |
Typical Software-Defined Radio Implementation
Figure 1 shows a typical software-defined radio (SDR) implementation. In this example, the major DSP portion of the design can be implemented in the Cyclone III LS EP3CLS200 device with enough head room to support currently available waveforms and next generation waveforms. A critical criteria is to meet performance needs while keeping size, weight, and power consumption to a minimum to extend battery life and reduce the size and weight of handheld equipment.
Figure 1. Typical Software-Defined Radio Block Diagram
Resources
Get to market faster, stay within power budgets, and increase your productivity over traditional design solutions with Cyclone III FPGAs. Table 2 provides links to just some of the resources available for designing military applications.
| Table 2. Design Resources | ||
| Category | Resource | Description |
|---|---|---|
| Development Kit Resources | ||
 |
Altera and partners offer a portfolio of development kits and application-specific daughtercards to jump-start any Cyclone III-based design. Each kit comes with everything you need to evaluate and design with Cyclone III FPGAs. You can order many of these kits via Altera's online eStore or any Altera® distribution partner. |
|
| Software and Intellectual Property Resources | ||
 |
Reference designs from Altera and partners for common wireless communications systems components such as scalable OFDMA reference design, digital down conversion (DDC) and digital up conversion (DUC), and bridges to DSP processors. | |
| Library of intellectual property (IP) cores from Altera and partners for the following DSP functional areas: filtering, modulation, demodulation, transforms encryption, decryption, correlation, error detection, error correction, signal generation, synchronization, and video and image processing. | ||
| The world's most versatile processor supported by easy-to-use development tools and a portfolio of FPGA development kits. | ||
| Video-on-Demand Resources | ||
 |
Partitioning FPGA Designs for Redundancy and Information Security |
Learn how to design fault-tolerant logic within a single FPGA, using the new design separation software feature in Quartus II software. Includes a short (about seven minutes) software demonstration. |
Addressing SWaP Constraints in Military and Aerospace Applications |
Learn how you can use the newest 65-nm FPGAs to reduce size, weight, and power in SWaP-constrained applications to take new platforms to the battlefield and air. | |
| White Papers | ||
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Learn how the latest FPGA security features protect IP from common threats (such as counterfeiting, reverse engineering, and cloning) to FPGA-based electronics. |
|
Designing With Confidence for Military SDR Production Applications (PDF) |
Describes how FPGAs can enable new SDR systems with smaller footprints, lighter weight, and smaller batteries. | |
Architecture and Component Selection for SDR Applications (PDF) |
Describes the objectives and trade-offs used to select components for battery powered SDRs to meet SWaP requirements. | |
Related Links
- Application Note 567: Quartus II Design Separation Flow (PDF)
- View the Cyclone III FPGA Design Resource Center and Literature Center
- View Altera's Military applications website
